Physical Verification Engineer

HCLTech; Redmond; Remoto; AUD 136.000 - 276.000; Tempo pieno

Vantaggi offerti da questo lavoro

Medical insurance

Dental insurance

Vision insurance

401(k) plan

Paid time off

Paid holidays

Descrizione del lavoro

HCLTech in Redmond, WA is seeking a highly talented Physical Verification Engineer to ensure IC layout correctness, foundry compliance, and manufacturability before tape-out. You will own DRC, LVS, ERC, DFM, antenna and density checks and drive issues to closure, collaborating with design, layout and foundry teams.

The role includes scripting for PV automation, runset customization, and support for final tape-out packages.

Competenze

• Strong hands-on experience with Physical Verification and layout signoff.
• Expertise in Calibre DRC, LVS, PERC, and DFM.
• Strong experience in DRC/LVS debugging and closure.
• Good understanding of IC layout design, physical verification methodologies, and semiconductor process rules.
• Experience with antenna, density, ERC, and DFM checks.
• Experience with runset customization and foundry rule deck interpretation.
• Hands-on experience supporting tape-out and signoff activities.
• Strong Linux/Unix and scripting skills, such as Tcl, Perl, Python, or Shell.
• Strong debugging and root-cause analysis capabilities.

Mansioni

• Perform DRC, LVS, and ERC verification and drive issues through final signoff.
• Execute physical verification using Siemens Calibre, including DRC, LVS, PERC, and DFM.
• Perform antenna and density checks and resolve violations.
• Own layout signoff management and ensure physical verification closure before tape-out.
• Debug complex DRC/LVS violations and perform root-cause analysis.
• Customize and maintain runsets/decks based on project and foundry requirements.
• Interpret foundry process technology rules and translate them into verification requirements.
• Perform DFM compliance checks to ensure layout manufacturability.
• Work closely with layout, physical design, and circuit design teams to resolve verification issues.
• Interact with foundry teams for rule interpretation and clarification.
• Support preparation and validation of the final tape-out package.
• Develop scripts and automation to improve physical verification and debug efficiency.

Conoscenze

Physical verification

Calibre DRC/LVS/PERC/DFM

Antenna checks

Density checks

Scripting (Python/Tcl/Perl/Shell)

Tape-out support

Linux/Unix

Runset customization

Foundry rule interpretation

Debugging/root-cause analysis

Strumenti

Calibre

Synopsys IC Validator (ICV)

Descrizione del lavoro

HCLTech is looking for a highly talented and self-motivated Physical Verification Engineer to join it in advancing the technological world through innovation and creativity.

Job Title: Physical Verification Engineer

Job ID: 154847

Position Type: Full Time

Location: Redmond, WA - Remote

We are looking for an experienced Physical Verification Engineer responsible for ensuring IC layout correctness, foundry compliance, and manufacturability before tape-out through complete physical verification and signoff.

The engineer will own DRC, LVS, ERC, DFM, antenna, and density verification, drive violations to closure, and work closely with design, layout, and foundry teams.

Key Responsibilities

• Perform DRC, LVS, and ERC verification and drive issues through final signoff.
• Execute physical verification using Siemens Calibre, including DRC, LVS, PERC, and DFM.
• Perform antenna and density checks and resolve violations.
• Own layout signoff management and ensure physical verification closure before tape-out.
• Debug complex DRC/LVS violations and perform root-cause analysis.
• Customize and maintain runsets/decks based on project and foundry requirements.
• Interpret foundry process technology rules and translate them into verification requirements.
• Perform DFM compliance checks to ensure layout manufacturability.
• Work closely with layout, physical design, and circuit design teams to resolve verification issues.
• Interact with foundry teams for rule interpretation and clarification.
• Support preparation and validation of the final tape-out package.
• Develop scripts and automation to improve physical verification and debug efficiency.

Required Qualifications

• Strong hands-on experience with Physical Verification and layout signoff.
• Expertise in Calibre DRC, LVS, PERC, and DFM.
• Strong experience in DRC/LVS debugging and closure.
• Good understanding of IC layout design, physical verification methodologies, and semiconductor process rules.
• Experience with antenna, density, ERC, and DFM checks.
• Experience with runset customization and foundry rule deck interpretation.
• Hands-on experience supporting tape-out and signoff activities.
• Strong Linux/Unix and scripting skills, such as Tcl, Perl, Python, or Shell.
• Strong debugging and root-cause analysis capabilities.

Nice to Have

• Experience with Synopsys IC Validator (ICV).
• Experience working directly with semiconductor foundries on rule clarification and signoff issues.
• Experience with advanced technology nodes and complex SoC designs.

Pay and Benefits

Pay Range Minimum: $95000/Year

Pay Range Maximum: $192000/Year

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to [e-mail] for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies:

• medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance
• employee assistance program
• 401(k) retirement plan
• 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year)
• and 10 paid holidays per year

How You’ll Grow

At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.