Senior Verification Enigneer

ic resources; Dornbirn; Vor Ort; EUR 65 000 - 85 000; Vollzeit

Zusammenfassung

A leading chip design house in Austria is seeking a Senior Verification Engineer to join their dynamic international team. The successful candidate will contribute to innovative ASIC projects across multiple industries including automotive and wireless, and collaborate closely with teams throughout Europe. This role offers a unique opportunity to work on technically challenging tasks while being part of a specialized engineering environment.

Qualifikationen

• Experience in UVM is required.
• Proven track record in complex ASIC projects.
• Knowledge of Verilog or SystemVerilog is essential.
• Fluency in English is mandatory.

Aufgaben

• Work on complex ASIC design projects.
• Collaborate with international teams in various engineering sectors.

Kenntnisse

UVM

Verilog

SystemVerilog

RTL design

English proficiency

Jobbeschreibung

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Senior Verification Engineer - Specialised ASIC Design House - West Austria

A successful chip design house in Austria is looking to hire a Senior Verification Engineer to join their international team.

They offer a wide range of specialised Engineering services used in automotive, audio, industrial, security, and wireless markets. You will have the opportunity to work on complex and challenging projects, collaborating closely with other teams in Europe.

Key Skills:

• Experience in UVM
• Worked on successful and complex ASIC projects
• Knowledge of a programming language (Verilog or SystemVerilog)
• Understanding of RTL design
• Fluent in English

If you are interested in applying or would like to find out more, please contact Lucy Edmondson.