Digital Design Engineer (Senior to Principal Level)

European Tech Recruit; Villach; Hybrid; EUR 75 000 - 100 000; Vollzeit

Zusammenfassung

A leading global semiconductor company in Villach is seeking a Digital Design Engineer at the senior to principal level. This role offers the chance to work on innovative digital design solutions, shaping IP block architectures and ensuring high performance. Ideal candidates will have extensive experience in digital design and be adept at collaboration within multi-disciplinary teams. Hybrid work model is available, with onsite presence required two days per week.

Qualifikationen

• 6 to 15 years of experience in digital design, preferably in the semiconductor sector.
• Solid understanding of DSP architectures.
• Strong RTL design and verification fundamentals.

Aufgaben

• Define and capture specifications for digital IP components.
• Architect and implement high-performance microarchitectures.
• Design RTL using industry-standard tools and methodologies.

Kenntnisse

Digital Design

RTL Design

DSP Architectures

Static Timing Analysis

Verification Fundamentals

Jobbeschreibung

Digital Design Engineer (Senior to Principal Level)

Location: Villach, Austria (Hybrid – 2 Days Onsite Per Week)

Join a leading global semiconductor company at the forefront of innovation. We’re looking for a highly capable Digital Design Engineer - from Senior to Senior Principal level - to contribute to advanced digital design solutions supporting capacitive and touch sensing technologies, as well as complex mixed-signal IPs.

About the Role:

Based in their Villach location, you'll work as part of a collaborative and skilled team focused on cutting-edge digital design. You'll be instrumental in shaping the architecture and development of IP blocks, leveraging your deep technical knowledge to impact real-world products.

Key Responsibilities:

• Define and capture specifications for digital IP components
• Architect and implement high-performance microarchitectures
• Design RTL using industry-standard tools and methodologies
• Drive design quality using Synthesis, Static Timing Analysis (STA), CDC, Lint, MVRC, and UPF flows

What You Bring:

• 6 to 15 years of experience in digital design, preferably in the semiconductor sector
• Solid understanding of DSP architectures and practical design experience
• Strong RTL design and verification fundamentals
• Ability to work efficiently across multi-disciplinary teams

Interested to know more?

Apply here with your CV .

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