Analog Mixed Signal Verification Engineer

TN Austria; Österreich; Vor Ort; EUR 50 000 - 90 000; Vollzeit

Zusammenfassung

Ein innovatives Unternehmen sucht erfahrene Analog & Mixed Signal Verification Engineers zur Entwicklung und Lieferung von IP-Lösungen. Diese Rolle bietet die Möglichkeit, in einem talentierten Team zu arbeiten und an herausfordernden Projekten zu arbeiten. Die Position erfordert umfangreiche Erfahrung in der AMS-Verifikation, einschließlich der Definition von Testplänen und der Implementierung von Testbenches mit System Verilog. Wenn Sie ein Teamplayer mit hervorragenden Kommunikationsfähigkeiten sind und bereit sind, Lösungen für internationale Kunden zu liefern, könnte dies die perfekte Gelegenheit für Sie sein.

Qualifikationen

• 5+ Jahre Erfahrung in AMS-Verifikation/Validierung.
• Kenntnisse in System Verilog und Verilog erforderlich.

Aufgaben

• Entwicklung und Lieferung von IP für Kunden.
• Definition und Implementierung von Testbenches für Mixed Signal Designs.

Kenntnisse

AMS Verification

System Verilog

Verilog

UNIX shell scripts

Communication Skills

Tools

Cadence-based AMS flow

Jobbeschreibung

Client:

Chipright

Location:

Job Category:

Other

EU work permit required:

Yes

Job Reference:

e7f0d38b101d

Job Views:

3

Posted:

20.04.2025

Expiry Date:

04.06.2025

Job Description:

Analog & Mixed Signal Verification Engineers

Chipright seeks highly motivated and experienced AMS Verification engineer to work in developing and delivering IP to our customers. This is a fantastic opportunity for talented engineers to work within a team of highly experienced engineers.

Requirements

1. 5+ years AMS Verification/Validation experience
2. Definition of MSDV plans for mixed signal chip designs, following the AMS requirement driven DV flow
3. Definition and implementation of top-level testbenches using System Verilog, test cases and verification attributes such as checkers, stimulus packages and similar components. UVM knowledge is a plus.
4. Develop behavioral models for analog blocks using Verilog, develop self-checking mixed-signal testbenches to verify and establish model vs. schematic equivalence
5. Fluency with Cadence-based AMS flow - Create test schematics, config views, ADE-L Interface, connect modules, Simulator options etc.
6. Must be comfortable with batch mode-based simulation bring-up
7. Ability to comprehend UNIX shell scripts
8. Debug test failures, follow up on design issues and drive to closure
9. Regular reporting of status, completion %, activities, risks, impediments, etc.

Desirable

1. A team player with good communication skills and previous experience in delivering solutions/services to a multi-national client

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