Verification Infrastructure Engineer- Testbench Architecture

AMD; Town of Fishkill (NY); On-site; USD 120,000 - 190,000; Full time

Job summary

AMD in Fishkill, NY is seeking an outstanding verification engineer to lead the transformation of Zen architecture verification infrastructure. You will develop reusable C++ libraries for stimulus generation, model checking, and scalable workflows while collaborating with CPU design, architecture, and CAD teams.

You will mentor teammates, guide verification methodology, and drive long-term infrastructure roadmaps to improve productivity across programs.

Qualifications

• Extensive experience in CPU, SoC, or IP Design Verification with strong understanding of modern DV methodologies and verification environments.
• Proven expertise developing verification infrastructure, frameworks, and reusable libraries using C++.
• Experience with stimulus generation, model checking, reference model development, and verification automation techniques.
• Strong knowledge of testbench architecture, verification scalability, and infrastructure modernization initiatives.
• Experience supporting complex processor or microarchitecture development programs from concept through product execution.
• Familiarity with AVF analysis, replacement initiatives, or related resilience and validation methodologies.
• Demonstrated ability to simplify complex verification flows and drive measurable productivity improvements across engineering teams.
• Strong software engineering skills, including object-oriented design, code quality, version control, and CI practices.
• Excellent collaboration, communication, and technical leadership skills with experience influencing cross-functional engineering organizations.

Responsibilities

• Lead the transformation and modernization of Zen architecture verification infrastructure by simplifying design verification (DV) methodologies and reducing verification development complexity.
• Architect, develop, and maintain reusable C++ verification libraries for stimulus generation, model checking, and scalable verification workflows.
• Drive productivity improvements Zen architecture and future processor programs through standardized, reusable verification frameworks and automation.
• Lead strategic infrastructure initiatives, including AVF replacement efforts and next-generation testbench modernization.
• Collaborate closely with CPU design, architecture, verification, and CAD teams to define and deploy scalable verification solutions.
• Identify opportunities to improve verification efficiency, testbench maintainability, and overall validation quality across multiple programs.
• Provide technical leadership and mentorship while influencing verification methodology, best practices, and long-term infrastructure roadmaps

Skills

Collaboration

Mentorship

Verification methodologies

Cross-functional teamwork

Education

BS or MS in CS or EE

Tools

C++

Verification frameworks

Stimulus generation

Model checking

Reference model development

CI/CD practices

Job description

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

The Role

We are looking for an outstanding candidate to provide technical expertise for execution on the functional verification strategy for our next generation microprocessor designs. You will maintain and improve existing functional verification methodology, improve existing infrastructure, and work on related projects and/or assignments as needed to meet team goals. Additionally, you will perform project definition, training and documentation. Finally, you will work with architects and TG/PG RTL/Designers and develop an effective working relationship with parties involved.

The Person

The ideal candidate will have good communication skills and the ability to work with a team with varied strengths. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

Key Responsibilities

• Lead the transformation and modernization of Zen architecture verification infrastructure by simplifying design verification (DV) methodologies and reducing verification development complexity.
• Architect, develop, and maintain reusable C++ verification libraries for stimulus generation, model checking, and scalable verification workflows.
• Drive productivity improvements Zen architecture and future processor programs through standardized, reusable verification frameworks and automation.
• Lead strategic infrastructure initiatives, including AVF replacement efforts and next-generation testbench modernization.
• Collaborate closely with CPU design, architecture, verification, and CAD teams to define and deploy scalable verification solutions.
• Identify opportunities to improve verification efficiency, testbench maintainability, and overall validation quality across multiple programs.
• Provide technical leadership and mentorship while influencing verification methodology, best practices, and long-term infrastructure roadmaps

Preferred Experience

• Extensive experience in CPU, SoC, or IP Design Verification with strong understanding of modern DV methodologies and verification environments.
• Proven expertise developing verification infrastructure, frameworks, and reusable libraries using C++.
• Experience with stimulus generation, model checking, reference model development, and verification automation techniques.
• Strong knowledge of testbench architecture, verification scalability, and infrastructure modernization initiatives.
• Experience supporting complex processor or microarchitecture development programs from concept through product execution.
• Familiarity with AVF (Architectural Vulnerability Factor) analysis, replacement initiatives, or related resilience and validation methodologies.
• Demonstrated ability to simplify complex verification flows and drive measurable productivity improvements across engineering teams.
• Strong software engineering skills, including object-oriented design, code quality, version control, and continuous integration practices.
• Excellent collaboration, communication, and technical leadership skills with experience influencing cross-functional engineering organizations.

Academic Credentials

• BS or MS with some industry experience desired (all degrees are related to CS or EE).

LOCATION:

Fishkill, NY

This role is not eligible for Visa Sponsorship

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.