Verification Engineer 1

Actalent; Mountain View (CA); Remote; Full time

Job summary

A leading company is seeking a Silicon Verification Engineer to create and implement verification plans for advanced AI chips. This fully remote position requires strong skills in Verilog, SystemVerilog, and UVM, along with effective communication and teamwork abilities. The role involves defining verification environments and supporting post-silicon verification activities. Competitive pay and comprehensive benefits are offered.

Benefits

Medical, dental & vision

401(k) Retirement Plan

Life Insurance

Short and long-term disability

Health Spending Account (HSA)

Transportation benefits

Employee Assistance Program

Time Off/Leave

Qualifications

• Minimum 2 years of experience with SystemVerilog and UVM.
• Experience in pre and post silicon verification test flow.

Responsibilities

• Define and implement a UVM verification environment.
• Run tests on RTL and Gate Level Netlists, debug failures.

Skills

Verilog

Communication

Collaboration

Teamwork

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Bachelor's degree in Computer Science

Tools

SystemVerilog

UVM

Mixed Signal Verification

Design Verification Methodology

Job description

Join to apply for the Verification Engineer 1 role at Actalent

Job Title: Silicon Verification Engineer

Job Description

The Silicon Verification Engineer will play a crucial role in the test-plan generation process, creating, testing, and implementing various verification plans for advanced chips used in AI products.

Responsibilities

1. Define, document, and implement a UVM verification environment, including agents and scoreboards.
2. Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral.
3. Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes.
4. Support post-silicon verification activities of the products, working with design and product teams.

Essential Skills

1. Proficiency in using Verilog and VMM/OVM/UVM.
2. Experience in pre and post silicon verification test flow and automated test benches.
3. Effective communication, collaboration, and teamwork skills.

Additional Skills & Qualifications

1. Minimum 2 years of experience with SystemVerilog and UVM.
2. Minimum 2 years of experience with Mixed Signal Verification.
3. Minimum 2 years of experience with Design Verification Methodology.
4. Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree.
5. Strong grasp of SystemVerilog and UVM.

Pay and Benefits

The pay range for this position is $30.00 - $40.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits may include:

• Medical, dental & vision
• Critical Illness, Accident, and Hospital coverage
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

Workplace Type

This is a fully remote position.

Application Deadline

This position is anticipated to close on May 21, 2025.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation, and speed to market. With a network of almost 30,000 consultants and more than 4,500 clients across the U.S., Canada, Asia, and Europe, Actalent serves many of the Fortune 500.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing due to a disability, please email [e-mail] for other accommodation options.