Test Architect – High-Speed I/O & ATE Infrastructure

Advanced Micro Devices; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

AMD is seeking an experienced Test Engineer to lead architecture, development, and integration of wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8. You will influence testability across Design for Test, Yield, and Manufacturing, improving quality and throughput.

You will mentor engineers, collaborate with global teams, and apply AI-enabled workflows to boost productivity. This senior role combines hands-on programming with technical leadership in a fast-paced

Qualifications

• Extensive Advantest V93000 test program development and debugging experience.
• Proficiency in Java and at least one additional programming or scripting language such as C++, Python, Perl, or shell scripting.
• Experience developing test flows, methods, patterns or vectors, timing, and diagnostics for manufacturing screens.
• Experience debugging hardware, software, device, and manufacturing interactions within wafer-sort or final-test environments.
• Linux/Unix proficiency with revision control and software-release practices.
• Experience with offline simulation tools (ORE) and leading test content development offline.

Responsibilities

• Contribute to the architecture, development, and integration of the wafer-sort Base Test Program and common Test Shell, including reusable services, configurations, test flows, diagnostics, data collection, release controls, and product-integration interfaces.
• Lead SmarTest 8 and Advantest V9300 test program infrastructure development, debug, validation, release readiness, and production support.
• Define scalable architecture and coding practices that enable reuse across products, derivatives, silicon revisions, test insertions, and manufacturing sites.
• Lead or co-lead wafer-sort test strategy, first-silicon bring-up, characterization, margining, screening, diagnostics, and failure isolation for high-speed I/O and die-to-die interfaces.
• Integrate patterns, vectors, timing, levels, test methods, device configurations, binning, data collection, and debug capabilities into the common test program.
• Debug complex interactions across silicon, test software, tester hardware, probe hardware, patterns, timing, and manufacturing processes.
• Partner with Design, Design for Test, Product Engineering, Yield Engineering, Test Hardware, and Manufacturing teams to identify coverage gaps, improve testability, and resolve product and production risks.
• Drive improvements in test quality, manufacturing yield, test time, maintainability, correlation, and release discipline.
• Lead technical reviews, document architectural decisions, mentor engineers, and influence infrastructure direction across project and functional boundaries.
• Support geographically distributed engineering teams, outsourced semiconductor assembly and test partners, and equipment vendors throughout development and high-volume manufacturing.

Skills

Advantest V93000

SmarTest 8

Java

C++

Python

Linux/Unix

Jira

Confluence

High-speed SerDes

Team leadership

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or Computer Science

Typically 7+ years of semiconductor product-development and ATE test-engineering experience

Tools

Advantest V93000

SmarTest 8

Git

Azure DevOps / GitHub / GitLab

Job description

AMD is seeking an experienced Test Engineer to lead architecture, development, and integration of wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8. You will influence testability across Design for Test, Yield, and Manufacturing, improving quality and throughput.

You will mentor engineers, collaborate with global teams, and apply AI-enabled workflows to boost productivity. This senior role combines hands-on programming with technical leadership in a fast-paced