System Performance Modeling Engineer

Qualcomm; San Diego (CA); On-site; USD 115,600 - 173,400; Full time

Benefits offered by this job

Annual discretionary bonus

Annual RSU grants

Competitive benefits package

Job summary

Qualcomm is looking for an individual to join their Infrastructure IP Team, working on system and platform architecture related to next-generation SoCs. The role involves significant exploration of NoC topology and memory architecture while collaborating with various teams to drive performance improvements.

With a prerequisite of a Bachelor’s degree in relevant fields, candidates should have 2–5 years experience or strong internships. A knowledge of related interconnect protocols and object-oriented programming is essential.

Qualifications

• Degree in Microelectronics, Computer Science, or related field required.
• 2–5 years of experience in SoC modeling or software development preferred.
• Understanding of AHB/AXI/ACE/ACE-Lite protocols beneficial.

Responsibilities

• Participate in NoC topology and memory architecture exploration.
• Drive architecture-oriented performance evaluations.
• Develop tools for architecture validation and exploration.

Skills

Computer architecture understanding

NoC architecture knowledge

C++ programming

Python programming

Communication skills

Data science knowledge

Education

Bachelor’s degree in Microelectronics, Computer Science, or related field

Tools

Programming tools

Job description

Overview

Qualcomm Technologies, Inc. is a leading technology innovator that drives the transformation of communication and data processing to create a smarter, connected future. The Infrastructure IP Team focuses on the definition and design of platform infrastructure hardware components such as Interconnect (NoC), System Cache, Memory Controllers and System MMU used in all Qualcomm SoCs. This role centers on system and platform architecture, with a strong emphasis on NoC topology architecture and system memory architecture, and involves architecture‑oriented performance explorations, power modeling and data‑driven simulations.

Responsibilities

• Participate in NoC topology and system memory architecture exploration campaigns, collaborating with key architects from various teams to analyze complex datasets and identify insights that shape next‑generation SoCs.
• Drive architecture‑oriented performance and power explorations across platform‑level components including NoC, memory subsystem, system cache and memory controllers.
• Develop new tools for architecture validation and exploration, focusing primarily on performance and power modeling with additional support for high‑level functional validation.
• Support exploratory methodology projects involving machine learning and data science.
• Expand, maintain, and document innovative modeling frameworks and help define new hardware modeling semantics, moving beyond conventional hardware programming languages.

Skills and Experience

• Robust understanding of computer architecture, memory hierarchy, and system/platform architecture.
• Experience or knowledge of NoC (Network‑on‑Chip) architecture, topologies, and design trade‑offs.
• Strong knowledge of object‑oriented programming (C++, Python) and programming paradigms.
• Knowledge of bus components, interconnect micro‑architecture, and interconnect protocols such as AHB/AXI/ACE/ACE‑Lite.
• Understanding of performance/power/area trade‑offs.
• Ability to quickly react and adapt to changes.
• Excellent communication skills.
• Experience in data science or machine learning (desired).

Requirements

• Degree in Microelectronics, Computer Science, or a related field.
• Preferably 2–5 years of solid experience in SoC modeling and/or software development; new graduates with strong internships and motivation will also be considered.
• Understanding of interconnect protocols (AHB/AXI/ACE/ACE‑Lite) and NoC concepts and topologies.
• Experience driving architecture‑oriented performance and power investigations on blocks such as NoC, memory controller, system cache, CPU, GPU, and multimedia is a plus.

Preferred Qualifications

• Master’s or PhD degree in Microelectronics, Computer Science, or a related field.
• Strong mathematical background.
• Knowledge of NoC architecture and network traffic engineering.
• Knowledge of Memory Controller, LPDDR & DDR protocols.

Minimum Qualifications

• Bachelor’s degree in Science, Engineering, or a related field and 2+ years of ASIC design, verification, validation, integration, or related experience.
• Master’s degree in Science, Engineering, or a related field and 1+ year of ASIC design, verification, validation, integration, or related experience.
• PhD in Science, Engineering, or a related field.

Equal Opportunity and Accessibility Statement

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. Qualifying individuals may email disability‑[e-mail] or call Qualcomm’s toll‑free number for assistance. Qualcomm also commits to making its workplace accessible for individuals with disabilities.

Pay Range and Benefits

Pay range: $115,600.00 – $173,400.00. In addition to base salary, this role may qualify for a competitive annual discretionary bonus program and annual RSU grants. Qualcomm offers a highly competitive benefits package designed to support employees at work, at home, and at play.