Strategic EDA Workflow Architect for Next-Gen Chips

NVIDIA Corporation; Santa Clara (CA); Híbrido; USD 184.000 - 288.000; Jornada completa

Descripción de la vacante

NVIDIA is seeking an EDA Workflow Optimization engineer in Santa Clara, CA to partner with global engineering teams and optimize the full chip design workflow from inception to production. You will build scalable tools and metrics that enable engineers to work faster while improving reliability and quality.

In this role you’ll apply UNIX, Python, Shell scripting, and EDA tooling expertise to drive data‑driven decisions, reduce cycle times, and contribute to next‑generation chip development in a

Formación

• Strong experience investigating and debugging complex, multi‑discipline problems in a UNIX engineering environment.
• Hands‑on experience with architectural decisions in technologies (storage, networking, compute) our chip engineers depend on.
• Experience with ASIC, VLSI, CAD/EDA or mixed signal design workflow environments.
• Hands‑on experience with EDA tools.
• Experienced in UNIX Systems programming and automation using Python and/or Shell.
• Authoritative level usage of UNIX and UNIX utilities.
• Excellent planning and communication skills.
• Experience in applying data analysis principles and influencing data‑driven decisions.
• Flexibility/adaptability working in a dynamic environment with changing requirements.
• BS in Computer Science or equivalent experience; MS (preferred).
• 5+yrs of relevant experience.

Responsabilidades

• Work in a diverse team performing fast paced investigations to empower our engineers to develop at the speed of light.
• Participate in the full life-cycle of tool development, test, and deployment.
• Work closely with other team members and chip engineers to understand and optimize how workflows use the compute and storage environments.
• Build metrics that are reliable and easy to use by hundreds of engineers around the world.
• Continuously improve our chip development process.
• Directly contribute to the overall quality and time to market for our next generation chips.

Conocimientos

UNIX engineering

Python

Shell

C/C++

Perl

EDA tools

Job schedulers

LSF

SLURM

GPU workloads

Distributed systems

Educación

BS in Computer Science

MS preferred

Herramientas

EDA tools

Descripción del empleo

NVIDIA is seeking an EDA Workflow Optimization engineer in Santa Clara, CA to partner with global engineering teams and optimize the full chip design workflow from inception to production. You will build scalable tools and metrics that enable engineers to work faster while improving reliability and quality.

In this role you’ll apply UNIX, Python, Shell scripting, and EDA tooling expertise to drive data‑driven decisions, reduce cycle times, and contribute to next‑generation chip development in a