STCO PDK Development and Custom Layout Integration Engineer (Hsinchu)

Qualcomm; Oregon (IL); On-site; USD 100,000 - 140,000; Full time

Job summary

A leading company in semiconductor technology is seeking an engineer to design test chips and support advanced silicon components. The role involves collaboration on technology integration and requires expertise in custom layouts along with adequate experience in layout design tools. Join a committed team driving innovation in the industry.

Qualifications

• 4+ years designing custom layouts in relevant domains
• Experience with layout design and verification tools
• Strong foundation in semiconductor technology

Responsibilities

• Design and layout of test chips for heterogeneous integration
• Technology benchmarking and PDK development
• Custom layout analysis and debugging

Skills

Mask layout

Physical design

SVRF scripting

Test chip design

PDK development

DFM development

Custom layout

Education

Bachelor's degree in Electrical Engineering

High School diploma

Tools

Cadence

Job description

Company:

Qualcomm Semiconductor Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Key Responsibilities

• Design and mask layoutof test chips for heterogeneous integration, custom DRAM, silicon components, and passive device development.

• Technology benchmarking, design flow, and PDK development for heterogeneous integration.

• Foundry interfaceand design support for System-Technology Co-Optimization (STCO).

• Layout and design analysis for advanced technology benchmarks

• Custom layout analysisfor product issue debugging.

Desired Skillset/Experience

• Mask layout, OPC experience
• Physical design and layout experiencein sub-10nm silicon technology; hybrid-bonding, u-bump, RDL, and advanced packaging-related work experience is a plus.
• SVRF and TCLscripting.
• Test chip design and executionexperience.
• PDK development experience(PEX, DRC, LVS).
• DFM development experience.
• Custom layoutexperience (Calibre, Cadence).
• Process integration and unit process developmentexperience is a strong plus.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR
High School diploma or equivalent and 8+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.

• 4+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).

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