Staff Yield Engineer - Foundry Yield Leader

Intel; Austin (TX); Hybrid; USD 156,000 - 255,000; Full time

Benefits offered by this job

Hybrid work model

Competitive compensation

Stock bonuses

Health benefits

Retirement plans

Vacation

Job summary

Intel is seeking a Foundry Technology Development Staff Yield Engineer to lead semiconductor yield activities from design to HVM. You will collaborate with Intel Foundry Services, TD, and Product Integration to define yield goals and roadmaps, track inline metrics, and develop models to reduce losses across logic, SRAM, and related devices on customer silicon.

The role involves engaging with internal teams and external customers, leading DOE studies, and driving for solutions that optimize yield

Qualifications

• Bachelor’s Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering or other relevant field with 6+ years of experience.
• Master's Degree with 4+ years of relevant experience.
• PhD with 2+ years of industry experience in the field.

Responsibilities

• Serve as the yield point of contact through design to High Volume Manufacturing (HVM).
• Define yield goals and roadmaps with cross-functional teams including IFS and TD.
• Identify yield detractors and lead improvement opportunities with TD and Lab teams.
• Develop yield models to identify parametric losses and support elimination of systematic losses.
• Lead investigations and root-causing on yield signals for customer silicon.

Skills

Yield analysis

Root cause analysis

Customer collaboration

Data interpretation

Inline inspection

Education

Bachelor’s Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering

Master's Degree in Electrical Engineering, Materials Science, Physics, Chemical Engineering

PhD in Electrical Engineering, Materials Science, Physics, Chemical Engineering

Tools

DOE methods

Statistical analysis

Job description

Intel is seeking a Foundry Technology Development Staff Yield Engineer to lead semiconductor yield activities from design to HVM. You will collaborate with Intel Foundry Services, TD, and Product Integration to define yield goals and roadmaps, track inline metrics, and develop models to reduce losses across logic, SRAM, and related devices on customer silicon.

The role involves engaging with internal teams and external customers, leading DOE studies, and driving for solutions that optimize yield