Staff Physical Design Engineer, Timing

Acara Solutions, An Aleron Company; Austin (TX); On-site; USD 106,500 - 162,000; Full time

Job summary

A leading company is seeking a Staff Engineer in Timing Methodology to transform designs into silicon reality. This role involves timing closure at both block and SOC levels, requiring collaboration with various teams and expertise in modern FinFET technologies. The ideal candidate will have a Master's degree and substantial experience in timing analysis, along with proficiency in industry-standard tools.

Qualifications

• Minimum of 5 years of experience in Timing Analysis and convergence.
• Proven expertise in static timing analysis using industry standard timing tools.

Responsibilities

• Own all aspects of timing convergence including signoff and timing analysis.
• Collaborate with RTL designers and other stakeholders for best PPA.

Skills

Analytical Skills

Problem-Solving

Teamwork

Communication

Education

Master's degree in Electrical Engineering

Tools

Cadence Tempus

Synopsys Primetime

TCL

Python

Fusion Compiler

Innovus

Job description

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As a Staff Engineer Timing Methodology, you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well.

Responsibilities:

• In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime.
• Own all aspects of the timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power.
• Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of Ips, namely, hard IP, Stdcell and Memory etc.
• Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si.
• Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA.
• Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of advancements in STA and new process nodes

Qualifications:

• Master's degree in Electrical Engineering or Computer Engineering (or a related field)
• Minimum of 5 years of experience in Timing Analysis and convergence.
• Proven expertise in static timing analysis using industry standard timing tools like primetime (Synopsys) or tempus (Cadence).
• In-depth understanding of digital circuit design principles and concepts
• Strong proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence)
• Excellent analytical and problem-solving skills
• Ability to work effectively in a team environment and communicate complex technical concepts clearly
• Experience with scripting languages (e.g., TCL, Python)
• Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence) is a plus.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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