Staff Package Design Engineer

Renesas Electronics; Tempe (AZ); On-site; USD 180,000 - 240,000; Full time

Job summary

Renesas Electronics Corp. is seeking a Staff packaging architect to guide the architecture and physical design of next‑generation semiconductor packages, including 2.5D/3D chiplet integration and high-density interposers.

You will coordinate across SI/PI, thermal, and platform teams and drive new design rules and methodologies. As a technical focal point, you will mentor junior engineers, establish standardized CAD workflows, and lead design reviews to balance electrical and mechanical

Qualifications

• 8+ years of related experience with a Bachelor’s degree (or 6+ years with a Master’s degree); OR 5+ years of intensive R&D experience in advanced 2.5D/3D heterogeneous packaging with demonstrated experience establishing new design rules and authoring engineering BKMs.
• Advanced Packaging Expertise: Strong background in advanced substrate-based packages, flip-chip layout, multi-die/chiplet-based architectures, thermal mitigation, and high-density routing.
• CAD Proficiency: High proficiency with industry-standard package design tools, specifically Siemens/Mentor Xpedition (Layout / Substrate Integrator), Valor NPI, and Cadence Allegro Package Designer/SIP Layout.
• Cross-Disciplinary Acumen: Working understanding of SI/PI fundamentals, impedance control, crosstalk mitigation, and ability to balance these constraints against pin budgets.
• Leadership & Communication: Strong communication and technical documentation skills, with a proven ability to lead multi-disciplinary test vehicles or product design meetings and secure tooling/supplier approvals independently.

Responsibilities

• Lead package layout architecture for next-generation heterogeneous integration, including 2.5D/3D chiplet packaging, high-density interposers, bridge technologies, RDL, and advanced FCBGA solutions.
• Define, establish, and optimize package design rules and assembly BKMs; partner with foundries, substrate vendors, and OSATs to evaluate and validate advanced packaging capabilities, DRCs, and manufacturing limits.
• Act as the primary package architecture focal point across SI/PI, thermal, tooling, and platform integration teams; lead design reviews to align requirements and balance pin budgets against electrical/mechanical trade-offs.
• Manage the complex package design cycle—including footprint assignment, stack-up structures, high-speed escape routing, power/ground distribution, and generation of manufacturing release outputs (Gerber/drill data, bump maps, assembly drawings).
• Provide technical mentorship and guidance to junior and intermediate package design engineers, establishing standardized CAD workflows, layout techniques, and training to drive consistent execution.

Skills

Advanced packaging

Leadership

Cross-disciplinary acumen

CAD proficiency

Communication

Education

Bachelor's or Master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or related discipline

Tools

Siemens Mentor Xpedition

Valor NPI

Cadence Allegro Package Designer

Job description

In this role, you will work at the intersection of IC design, advanced package development, and system-level implementation. As a Staff-level contributor, you will serve as the technical focal point, guiding the architecture and physical design of next-generation, high-performance semiconductor packages, including 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies.

This role requires deep expertise in advanced packaging R&D, cross-domain co-design, and the ability to define methods and procedures for complex, multi-die integration assignments. You will lead cross-functional alignment with global silicon design, signal integrity/power integrity (SI/PI), thermal, and product engineering teams, while driving the creation of new packaging design rules and methodologies.

Key Responsibilities

• Physical Architecture Leadership: Lead package layout architecture and physical design for next-generation heterogeneous integration, including 2.5D/3D chiplet packaging, high-density interposers, bridge technologies (e.g., EMIB equivalents), RDL, and advanced FCBGA solutions.
• Methodology & Design Rules: Define, establish, and optimize package design rules and assembly Best Known Methods (BKMs); partner with foundries, substrate vendors, and OSATs to evaluate and validate advanced packaging capabilities, DRCs, and manufacturing limits.
• Cross-Functional Technical Focal Point: Act as the primary package architecture lead across SI/PI, thermal, tooling, and platform integration teams. Lead design reviews to establish project scope, align stakeholder requirements, and balance pin budgets against electrical and mechanical trade-offs.
• Layout & Release Management: Manage the complex package design cycle—including footprint assignment, stack-up structures, high-speed escape routing, power/ground distribution, and generation of manufacturing release outputs (Gerber/drill data, bump maps, assembly drawings).
• Mentorship: Provide technical mentorship and guidance to junior and intermediate package design engineers, establishing standardized CAD workflows, layout techniques, and technical training to drive consistent execution across the department.

In this role, you will work at the intersection of IC design, advanced package development, and system-level implementation. As a Staff-level contributor, you will serve as the technical focal point, guiding the architecture and physical design of next-generation, high-performance semiconductor packages, including 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies.

This role requires deep expertise in advanced packaging R&D, cross-domain co-design, and the ability to define methods and procedures for complex, multi-die integration assignments. You will lead cross-functional alignment with global silicon design, signal integrity/power integrity (SI/PI), thermal, and product engineering teams, while driving the creation of new packaging design rules and methodologies.

Job Description

In this role, you will work at the intersection of IC design, advanced package development, and system-level implementation. As a Staff-level contributor, you will serve as the technical focal point, guiding the architecture and physical design of next-generation, high-performance semiconductor packages, including 2.5D/3D heterogeneous integration, chiplet-based architectures, high-density interposers, and advanced substrate technologies.

This role requires deep expertise in advanced packaging R&D, cross-domain co-design, and the ability to define methods and procedures for complex, multi-die integration assignments. You will lead cross-functional alignment with global silicon design, signal integrity/power integrity (SI/PI), thermal, and product engineering teams, while driving the creation of new packaging design rules and methodologies.

Qualifications

Experience

• 8+ years of related experience with a Bachelor’s degree (or 6+ years with a Master’s degree); OR 5+ years of intensive R&D experience in advanced 2.5D/3D heterogeneous packaging (bridge/interposer architectures) with demonstrated experience establishing new design rules and authoring engineering BKMs.
• Advanced Packaging Expertise: Strong background in advanced substrate-based packages, flip-chip layout, multi-die/chiplet-based architectures, thermal mitigation, and high-density routing.
• CAD Proficiency: High proficiency with industry-standard package design tools, specifically Siemens/Mentor Xpedition (Layout / Substrate Integrator), Valor NPI, and/or Cadence Allegro Package Designer / SiP Layout.
• Cross-Disciplinary Acumen: Working understanding of SI/PI fundamentals, impedance control, crosstalk mitigation, and the ability to balance these constraints against pin budgets and platform integration requirements.
• Leadership & Communication: Strong communication and technical documentation skills, with a proven ability to lead multi-disciplinary test vehicle or product design meetings and secure tooling/supplier approvals independently.

Education

• Bachelor's or Master's degree in Mechanical Engineering, Electrical Engineering, Microelectronics, Materials Science, or a related technical discipline.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.