Staff Engineer, PCIe Silicon Enablement

Tenstorrent; California; Híbrido; USD 150.000 - 210.000; Jornada completa

Descripción de la vacante

Tenstorrent is seeking a versatile silicon enablement engineer to drive PCIe enablement across controller, PHY, board, SoC, and SiP, from pre-silicon planning through first-silicon bring-up and ongoing product support. You will develop firmware, tests, and reusable infrastructure, bring up root‑complex and endpoint behavior, and debug issues using a wide range of lab tools and protocol analyzers.

The role emphasizes collaboration across architecture, design, verification, firmware, systems, and

Formación

• Extensive PCIe experience across hardware, software, and systems.
• Hands-on in lab and in firmware development for silicon systems.
• Ability to debug complex silicon systems using lab tools and traces.

Responsabilidades

• Drive PCIe silicon enablement across controller, PHY, board, SoC, and SiP.
• Develop enablement plans, firmware, tests, automation, and reusable infrastructure.
• Bring up PCIe root‑complex and endpoint behavior including enumeration, link training, and power management.
• Debug hardware, firmware, and software issues using protocol analyzers, oscilloscopes, JTAG, and traces.
• Mentor engineers and turn post-silicon learnings into product improvements.

Conocimientos

PCIe experience

Firmware debugging

Lab tools usage

System bring-up

Protocol analysis

Herramientas

Oscilloscopes

JTAG

Trace tools

Descripción del empleo

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The Silicon Enablement Team drives first-silicon success by connecting architecture, design, verification, firmware, systems, and product teams throughout the silicon lifecycle. The team develops enablement plans, tests, firmware, and reusable infrastructure; brings up silicon and systems; investigates failures; and applies post-silicon learnings to improve products. Spanning IP, SoC, and SiP enablement, the work ranges from pre-silicon planning and tapeout through board and system bring-up, production firmware releases, and ongoing product support. This role combines firmware, automation, lab tools, and system-level debugging to solve complex problems and help shape the future of PCIe in AI/ML computing.

This role is hybrid and based in Santa Clara, California, Austin, Texas, Toronto, Canada or Vancouver, Canada.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You bring extensive PCIe experience across hardware, software, and systems, with a strong grasp of architecture and protocol behavior including link training and LTSSM, enumeration, configuration space, resets, and error recovery.
• You enjoy bringing hardware to life and solving complex problems across the hardware–software boundary, from pre-silicon planning and architecture alignment through first-silicon bring-up and product support.
• You are comfortable developing and debugging low-level firmware, automation, and reusable infrastructure for complex silicon systems, including PCIe controller and PHY bring-up.
• You are hands‑on in the lab and can investigate clocks, sideband signals, SerDes/PHY behavior, lane issues, and system interactions using tools such as oscilloscopes, protocol analyzers, exercisers, JTAG, and trace tools.
• You understand how PCIe integrates with platform firmware and software, including UEFI/BIOS, operating-system drivers, DMA, interrupts, and IOMMUs and you are curious, collaborative, and effective in a fast‑paced, output‑ and value‑driven environment.

What We Need

• Drive PCIe silicon enablement across controller, PHY, board, SoC, and SiP levels, from pre-silicon planning through first-silicon bring-up and ongoing product support.
• Develop enablement plans, firmware, tests, automation, and reusable infrastructure for functional behavior, performance, compliance, interoperability, and error recovery.
• Bring up and integrate PCIe root‑complex and endpoint behavior, including enumeration, link training and equalization, lane configuration, resets, power management, and configuration access.
• Debug failures across hardware, firmware, and software using protocol analyzers, exercisers, oscilloscopes, JTAG, logs, traces, error injection, and targeted experiments; collaborate across architecture, design, verification, firmware, systems, and product teams to drive root‑cause closure.
• Define a PCIe enablement roadmap and production‑readiness criteria, mentor engineers, and turn post-silicon learning into improvements in designs, firmware, enablement processes, and product quality.

What You Will Learn

• How silicon progresses from architecture and pre‑silicon planning through tapeout, first‑silicon bring‑up, system integration, and ongoing product support.
• How IP, SoC, SiP, boards, firmware, and system software come together to deliver a successful product.
• How to build silicon enablement plans, tests, firmware, and reusable infrastructure for next‑generation AI platforms.
• How to use lab tools, automation, logs, traces, and system‑level debugging to investigate failures and understand real silicon behavior.
• How to collaborate across architecture, design, verification, firmware, systems, and product teams and turn post‑silicon learning into better products in a fast‑moving engineering environment.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export‑controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.