Staff Engineer, PCIe PHY/Link Analysis

Socket.dev; San Jose (CA); On-site; USD 163,000 - 253,000; Full time

Benefits offered by this job

4+ weeks paid time off

Medical/Dental/Vision

Onsite gym/cafe

Job summary

Samsung Semiconductor in San Jose, CA seeks an engineer to develop and support PCIe host interface firmware for enterprise NVMe SSD products. You will work across PHY through Transaction/Transport layers, bringing up links and debugging LTSSM, with onsite field support and up to 25% travel.

Required: BS/MS in a relevant field and 8+ years of hardware/firmware experience, strong C/C++, and proficiency with PCIe protocol analyzers and JTAG/ICE debuggers.

Qualifications

• BS in Computer/Electrical/Electronic Engineering or CS; 8+ years hardware/firmware experience or MS with 5+ years.
• Deep proficiency with PCIe protocol from PHY to Transaction/Transport layers.
• Strong embedded C/C++ software experience and debugging skills.

Responsibilities

• Understand PCIe PHY/Link architecture and LTSSM; guide LTSSM training and enumeration.
• Analyze and validate TLP/DLLP handling, flow control, and error management (AER).
• Debug complex PHY/Link/Transport issues during bring‑up and NVMe SSD product life cycle.
• Support industry PCIe compliance tests and provide onsite field support.

Skills

PCIe protocol

Embedded C/C++

UART/JTAG/ICE

LTSSM

PCIe protocol analyzers

Logic analyzers

Signal analyzers

Education

BS in Computer/Electrical/Electronic Eng or CS

MS with 5+ years experience

Tools

PCIe protocol analyzers

Logic analyzers

Signal analyzers

Job description

Please Note:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together

Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.

We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

At the Technology Enabling Development Lab (TED), our core development focus is the host interface firmware layer that sits in the intersection of system software and flash management firmware. This key host interface firmware technology drives Samsung’s breakthrough V‑NAND technology and enables our customers to power performance-oriented, demanding, enterprise‑class applications ranging from hyper-scale data centers, to big data processing, to software defined virtualized storage arrays and infrastructures.

We are looking for a dynamic, self‑motivated engineer to develop and support our cutting‑edge Enterprise and Data Center SSD products. The ideal candidate will possess comprehensive expertise across the full PCIe protocol stack - from the Physical Layer (PHY) through the Data Link Layer and up to the Transaction/Transport Layer - with a proven track record in hardware/firmware design, protocol implementation, and complex link bring‑up and debugging. This position is based in San Jose, California.

What You’ll Do

• Protocol Stack Analysis: Understand PHY/Link architecture, implementation, and integration of the PCIe protocol stack from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer, in collaboration with internal H/W teams and external vendors.


• Link Bring‑up & Training: Own LTSSM behavior, link training and equalization sequencing, PCIe enumeration, and configuration‑space flows during device bring‑up.


• Transaction/Transport Layer: Analyze and validate TLP/DLLP handling, flow control, credit management, ordering rules, ACK/NAK and replay, error handling (AER), and end‑to‑end data integrity across the stack.


• Debug & Optimization: Analyze and debug complex PHY, Link, and Transport layer issues during bring‑up and sustaining stages of NVMe SSD products, from Gen1 to the latest generation (Gen7), covering protocol (LTSSM / PCIe enumeration) and PCIe feature‑related issues.


• Compliance & Standards: Participate in and support industry PHY/Link compliance tests, including PCI‑SIG events.


• Field Support: Provide onsite support for PHY/Link related tasks at customer sites and labs.


• Travel: This position requires up to 25% business travel.

What You Bring

• BS in Computer/Electrical/Electronic Engineering or Computer Science, and 8+ years of relevant experience in hardware or a MS in Computer/Electrical/Electronic Engineering or Computer Science with 5+ years of relevant experience is required.


• Protocol Expertise: Deep proficiency with the PCIe protocol spanning the entire architecture from the Physical Layer through the Data Link Layer to the Transaction/Transport Layer.


• Link Layer Mastery: Strong hands‑on knowledge of LTSSM, link training/equalization, PCIe enumeration, flow control, replay/retry, and error handling (AER).


• PHY Awareness: Working knowledge of PHY‑layer operation (CDR to Equalizer such as VGA, CTLE, DFE, FFE, DSP, etc ) sufficient to root‑cause link issues that cross the PHY/Link boundary.


• Firmware & Debugging: Solid experience in C/C++ for embedded systems, and expertise with UART/JTAG/ICE debuggers and general firmware debugging techniques.


• Analysis Tools: Strong experience with PCIe protocol analyzers, logic analyzers, and signal analyzers for link and transaction‑level debug.


• Collaboration: Ability to work effectively within a multi‑functional team environment.

Preferred Skills

• Knowledge on SI/PI for PCIe


• Extended Protocols: Proficiency in NVMe, CXL, or SAS/SATA protocols is a significant plus.


• Validation: Experience in both pre‑silicon and post‑silicon SoC validation.


• Power Management: Experience with PCIe power management (ASPM, L1 substates) and low‑power link states.

#LI-VL1

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job‑related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.

This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.

Give Back: With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.

Enjoy Time Away: You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.

Care for Family: Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.

Prioritize Emotional Wellness: With on‑demand apps and free confidential therapy sessions, you’ll have support no matter where you are.

Stay Fit: Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.

Embrace Flexibility: Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.

Base Pay Range

$163,000 — $253,000 USD

Equal Opportunity Employment Policy

Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.

When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long‑term conditions, neurodivergent individuals, or those requiring pregnancy‑related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.

Recruiting Agency Policy

We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.

Applicant AI Use Policy

At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we ask that candidates rely on their own knowledge and skills throughout the process. AI tools may be used for basic preparation, grammar, and research, but should not be used to generate or assist with submitted content or live interview responses. If we determine that AI is being used outside these guidelines, we reserve the right to pause or end the interview, and your candidacy may be disqualified.

Trade Secret Notice

By submitting an application, you agree not to disclose to Samsung—or encourage Samsung to use—any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

Applicant Privacy Policy

https://semiconductor.samsung.com/about-us/careers/us/privacy/