Staff Engineer, Hardware Test and Validation

Celestica; San Jose (CA); On-site; USD 135,000 - 210,000; Full time

Job summary

Celestica seeks a Staff Engineer, Hardware Test and Validation to lead validation and characterization of high-performance hardware platforms. The role blends hands-on measurement with strategic engineering decisions and cross-functional influence across SI, PI, PCIe, Ethernet, and SerDes across multiple programs.

The successful candidate will mentor teams, define validation methodologies, and guide architecture decisions while engaging with customers and partners to ensure robust validation

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• Typically 12+ years of hardware design, validation, SI/PI, or related experience.
• Deep understanding of high-speed digital design, impedance, reflections, jitter, and timing margins.
• Strong hands-on expertise with PCIe and Ethernet electrical validation and system-level debugging.

Responsibilities

• Define hardware validation strategies, methodologies, and acceptance criteria across programs.
• Lead hardware validation efforts for SI/PI, including channel design and lab measurements.
• Provide technical direction for schematics, PCB layout, and design-for-validation practices.
• Lead cross-functional reviews and mentor engineers across teams.

Skills

Signal Integrity

Power Integrity

PCIe

Ethernet

SerDes

Lab Measurement

Education

Bachelor's degree: Electrical Engineering

Tools

Oscilloscopes

VNAs

TDR/TDT

BERTs

Power Analyzers

Job description

Celestica is seeking a Staff Engineer, Hardware Test and Validation to provide senior technical and engineering leadership for the validation and characterization of complex, high-performance hardware platforms.

As a Staff Engineer, this individual will serve as a technical authority and leader across hardware validation, signal integrity, power integrity, and high-speed interface technologies. The role will define validation strategies, establish engineering methodologies and best practices, guide complex technical investigations, and influence product architecture and design decisions across multiple programs.

The successful candidate will combine deep hands-on expertise in signal integrity, power delivery and power integrity, PCI Express (PCIe), Ethernet, and high-speed SerDes technologies with the ability to lead and mentor engineering teams, influence cross-functional organizations, and engage technically with customers and technology partners.

This position requires an engineer who can move comfortably between detailed laboratory measurements, system-level architecture, technical leadership, and strategic engineering decisions.

Key Responsibilities

Technical Leadership and Strategy

• Serve as a technical authority for hardware test, validation, signal integrity, and power integrity across complex compute, networking, storage, and high-speed digital platforms.
• Define and drive comprehensive hardware validation strategies, methodologies, coverage models, and acceptance criteria across multiple products and programs.
• Establish engineering standards, validation methodologies, design-for-validation practices, and technical best practices that can be adopted across engineering teams.
• Provide technical direction for complex or ambiguous hardware problems where solutions require cross-disciplinary expertise.
• Influence product architecture and hardware design decisions by identifying SI, PI, interface, and system-level risks early in the product development lifecycle.
• Lead technical reviews and provide guidance on schematics, PCB architecture and layout, component selection, high-speed channel design, power delivery architecture, and validation strategy.
• Identify technology and capability gaps and drive improvements in laboratory infrastructure, equipment, automation, simulation-to-measurement correlation, and engineering processes.
• Represent hardware validation in major architecture, design, readiness, and product release reviews.

Signal Integrity and High-Speed Interface Validation

• Provide technical leadership for signal integrity characterization and validation of high-speed digital interfaces.
• Define and execute advanced characterization methodologies for eye diagrams, jitter, timing margins, BER, channel loss, impedance, reflections, crosstalk, and other high-speed electrical parameters.
• Lead electrical validation and troubleshooting of high-speed serial technologies including PCI Express (PCIe), Ethernet, SerDes, and other high-speed interconnects.
• Provide expertise across applicable generations of PCIe, including PCIe Gen5 and Gen6, transmitter/receiver characterization, link-margin analysis, equalization, compliance-oriented testing, and system-level debug.
• Lead validation of advanced Ethernet interfaces, including 100G, 200G, 400G, and 800G Ethernet technologies where applicable.
• Provide expertise in both NRZ and PAM4 signaling, including high-speed channel characterization and margin analysis.
• Lead VNA, TDR/TDT, S-parameter, and oscilloscope-based characterization of PCB channels, connectors, cables, and other interconnects.
• Correlate laboratory measurements with SI simulation results and work with design and simulation teams to improve predictive accuracy.

Power Integrity and Power Validation

• Define and lead power delivery and power integrity validation for high-performance systems.
• Characterize voltage regulation, ripple and noise, transient response, load regulation, power sequencing, rail stability, efficiency, and current consumption.
• Evaluate system power behavior under dynamic and worst-case workloads, including high-current CPU, GPU, FPGA, ASIC, accelerator, and memory power rails.
• Lead PDN characterization and measurement-to-simulation correlation.
• Identify system-level interactions between power integrity, signal integrity, thermal behavior, workload characteristics, and overall platform performance.
• Provide technical guidance on power architecture and validation requirements during early product development.

Hardware Debug and Root-Cause Analysis

• Lead the resolution of the organization's most challenging hardware and system-level technical issues.
• Drive structured root-cause analysis involving high-speed interfaces, PCB channels, power delivery networks, components, connectors, cables, firmware, and system-level interactions.
• Develop measurement strategies to isolate complex failures and distinguish between electrical, firmware, component, manufacturing, and system-level causes.
• Partner with hardware design, SI/PI, firmware, mechanical, thermal, manufacturing, quality, and supplier engineering teams to drive issues to resolution.
• Provide technical escalation support for critical customer and product issues.

Test Automation and Engineering Capability

• Drive development of scalable and repeatable validation environments using Python or similar automation frameworks.
• Establish approaches for automated instrumentation control, test execution, data acquisition, analysis, visualization, and reporting.
• Identify opportunities to improve engineering productivity through automation, standardized test platforms, and reusable validation infrastructure.
• Drive improved use of engineering data to identify trends, quantify design margin, and accelerate technical decision-making.

Engineering Leadership and Organizational Influence

• Provide technical leadership and mentorship to Senior Lead Engineers, hardware validation engineers, SI/PI engineers, and laboratory teams.
• Develop engineers through technical coaching, design and validation reviews, hands-on problem solving, and knowledge sharing.
• Lead cross-functional technical teams through complex investigations and major product development milestones.
• Create alignment across engineering disciplines when technical requirements or priorities conflict.
• Influence engineering decisions across multiple programs without relying solely on direct reporting authority.
• Build strong working relationships with customers, silicon vendors, equipment suppliers, and technology partners.
• Lead technical discussions with customers and partners on validation strategy, technical risks, test results, and corrective actions.
• Promote a culture of engineering rigor, data-driven decision-making, technical excellence, collaboration, and continuous improvement.
• Help establish technical roadmaps for future validation capabilities based on emerging high-speed interface, power, and system technologies.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline; Master's degree preferred.
• Typically 12+ years of progressive experience in hardware design, hardware validation, signal integrity, power integrity, electrical characterization, or related disciplines.
• Demonstrated experience operating as a senior technical leader on complex hardware development programs.
• Deep understanding of high-speed digital design and signal integrity, including transmission lines, impedance, reflections, insertion and return loss, crosstalk, jitter, equalization, BER, and timing margin.
• Strong hands-on expertise with PCIe and Ethernet electrical validation and system-level troubleshooting.
• Strong knowledge of high-speed SerDes architectures, NRZ and PAM4 signaling, and channel characterization.
• Deep understanding of power delivery and power integrity, including voltage regulation, PDN behavior, transient response, ripple/noise, sequencing, and high-current power rails.
• Extensive experience using high-bandwidth oscilloscopes, BERTs, VNAs, TDR/TDT equipment, spectrum analyzers, protocol analyzers, electronic loads, power analyzers, and other advanced laboratory instrumentation.
• Strong ability to interpret schematics, PCB layouts, design specifications, simulation results, standards, and component documentation.
• Demonstrated ability to lead complex root-cause investigations spanning multiple engineering disciplines.
• Experience with Python or similar programming/scripting languages for test automation and data analysis.
• Strong written and verbal communication skills with the ability to communicate complex technical subjects to engineering teams, senior leadership, customers, and partners.

Preferred Technical Experience

Experience in several of the following areas is highly desirable:

• PCIe Gen5/Gen6 electrical validation and compliance
• 100G/200G/400G/800G Ethernet
• Advanced SerDes characterization
• PAM4 and NRZ signaling
• Eye diagram, jitter, BER, bathtub-curve, and link-margin analysis
• S-parameter and VNA-based channel characterization
• TDR/TDT and impedance characterization
• High-speed PCB and connector characterization
• Power integrity and PDN simulation/measurement correlation
• High-current CPU, GPU, ASIC, FPGA, and accelerator power delivery
• Protocol and link-layer debugging
• Python-based laboratory automation and data analytics
• Server, networking, storage, AI/ML, or high-performance computing platforms
• Development and qualification of complex multi-board systems

Staff-Level Leadership Expectations

The Staff Engineer is expected to operate beyond the scope of an individual product or validation activity and provide technical leadership across programs, engineering teams, and technology areas.

Success in this role requires the ability to:

• Set technical direction rather than simply execute an established validation plan.
• Recognize cross-program technical risks and establish scalable solutions.
• Make and influence architecture-level engineering decisions based on measurement, analysis, and sound engineering judgment.
• Lead complex technical initiatives involving multiple engineering disciplines and organizations.
• Serve as an escalation point for the most difficult SI, PI, high-speed interface, and system-level hardware problems.
• Develop the technical capabilities of other engineers through mentoring and hands-on leadership.
• Communicate effectively with customers and senior technical stakeholders.
• Translate emerging technologies and customer requirements into validation capabilities and engineering roadmaps.
• Balance immediate product execution with longer-term improvements in engineering methodology, automation, laboratory capability, and organizational technical expertise.

The Staff Engineer will remain technically hands-on while providing broader leadership and influence, serving as a key bridge between detailed engineering execution, product architecture, customers, and the wider engineering organization.

Typical Education

Bachelor degree or consideration of an equivalent combination of education and experience.

Educational Requirements may vary by Geography

The salary range described in this posting is an estimate by the Celestica, and may change based on several factors, including by not limited to a change in the duties covered by the job posting, or the credentials, experience or geographic jurisdiction of the successful candidate. Salary Range: $135,000-$210,000