Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Engg; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Engg is seeking a Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU to lead architecture exploration and performance validation. The role focuses on next-generation CPU/RISC-V microarchitecture and contrasting workloads in data center and agentic AI contexts.

You will own microarchitectural domains, apply AI-assisted methodologies, and develop performance models and simulators, collaborating across teams to shape silicon design and publication

Qualifications

• Master's degree (or PhD) with 5+ years (PhD) or 8+ years (Master's) of relevant experience.
• 4+ years of experience in CPU microarchitecture or performance engineering.
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit.
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
• Hands-on experience with architectural simulators such as gem5.
• Proficiency in C/C++ and Python.
• Experience analyzing large-scale performance data and traces.

Responsibilities

• Propose new architecture ideas and take ownership of one or more microarchitectural domains (front-end, mid-end, back-end).
• Use AI-driven design methodologies to rapidly implement architectural ideas and validate them on real silicon.
• Build, extend, and validate performance models and architectural simulators.
• Perform CPI/IPC analysis and identify root causes of performance bottlenecks.
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models.
• Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces.
• Translate performance analysis and modeling results into architectural direction and design decisions.

Skills

C/C++

Python

Performance analysis

CPU microarchitecture

Architectural modeling

Education

Master's degree in Computer Engineering or Computer Science

PhD in a related field

Tools

gem5

Job description

Staff Engineer , Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.

Location: Daily onsite presence at our San Jose office in alignment with our Flexible Work policy

Job ID: 43004

What You'll Do

The Architecture Research Lab is focused on researching next-generation CPU (RISC-V) microarchitecture and performance for emerging computing workloads. We explore new architectural ideas, evaluate their performance potential, and rapidly turn promising concepts into working designs that can be validated on real silicon. Our research is driven by emerging opportunities in data center and agentic AI workloads, where we investigate how CPU architecture can evolve to meet new performance and efficiency requirements. We also explore CPU-memory co-design from the CPU perspective, in alignment with the broader shift toward memory-centric architectures. A distinctive aspect of our team is the way we approach architecture research. We develop and apply AI-driven methodologies to accelerate architectural exploration, broaden the design space we can investigate, and quickly iterate from ideas to implementation and silicon validation. Rather than simply following established design flows, we continuously seek new ways to explore, evaluate, and realize CPU architectures. The role offers an opportunity to work across the full spectrum of architecture research—from workload and performance analysis, microarchitectural innovation, and architectural modeling to implementation and silicon validation—while helping shape new methodologies for how future CPUs are designed.

• Propose new architecture ideas and take ownership of one or more microarchitectural domains, including front-end, mid-end, and back-end
• Use AI-driven design methodologies to rapidly implement architectural ideas and validate them on real silicon
• Build, extend, and validate performance models and architectural simulators
• Perform CPI/IPC analysis and identify root causes of performance bottlenecks
• Evaluate microarchitectural features and optimizations using trace-driven, analytical, and cycle-accurate models
• Characterize workloads and benchmarks, including SPEC, server, client, AI/ML, agentic AI, and internal traces
• Translate performance analysis and modeling results into architectural direction and design decisions
• Drive research leading to patents and technical publications

What You Bring

• Master's degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or PhD with 5+ years of relevant experience
• 4+ years of experience in CPU microarchitecture or performance engineering
• Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector unit
• Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems
• Hands-on experience with architectural simulators such as gem5
• Proficiency in C/C++ and Python
• Experience analyzing large-scale performance data and traces

You're inclusive, adapting your style to the situation and diverse global norms of our people. You approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change.

#LI-SF1

Preferred Qualifications

• Experience with AI-driven or agentic design workflows, including high-level design languages and AI-assisted RTL generation, or a strong interest in and ability to quickly learn such methods
• Understanding of agentic AI workload execution patterns
• Domain-specific experience in one or more of the following areas:
  • Front-end: Branch prediction and decoupled fetch, particularly for compiler- or interpreter-driven workloads
  • Mid-end: RVV/SIMD, matrix/tensor engine design, and out-of-order vector execution
  • Back-end: LSU/MSHR design and prefetcher design for irregular access patterns
• Experience with PPA trade-off analysis
• Experience leading and mentoring junior engineers
• Experience with CPU tapeout or silicon validation
• Experience with patents or technical publications

What We Offer

The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive