Staff Digital Design Engineer

Renesas; Chandler (AZ); On-site; USD 125,000 - 170,000; Full time

Job summary

Renesas Electronics in Chandler, AZ seeks a Staff Digital Design Engineer to design power and area-optimized digital circuits for advanced mixed-signal applications. You will lead digital design efforts, mentor engineers, and collaborate with analog and verification teams across the silicon development lifecycle.

Requirements include 10+ years in digital design, fluency in Verilog/SystemVerilog, and strong ASIC methodology.

Qualifications

• 10+ years of digital design experience in wireless handheld, data conversion, and power management.
• Degree-level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
• Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block-level & chip-level verification techniques.
• Strong & proven ability to debug both RTL & gate-level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Preferred: experience with Digital Signal Processing concepts and hardware realizations.
• Preferred: scripting experience and flow automation knowledge.
• Preferred: mixed-signal design methodologies and STA/timing closure knowledge.

Responsibilities

• Interpreting high level requirements to architect, design & integrate low-power digital circuits for mixed-signal data conversion and power management products.
• Support full product lifecycle from concept to mass-production and coordinate with silicon development teams.
• Provide technical leadership to the digital design team and mentor junior engineers.
• Collaborate with Analog and Verification engineers to deliver silicon solutions.
• Ensure digital development processes meet timelines, budget, and project goals.
• Design digital RTL to meet timing, area, and power constraints.
• Integrate design at top level and run block & top-level simulations.
• Participate in mixed-signal design flow: architecture, partitioning, timing, synthesis, and verification.
• Work with P&R team to generate layout meeting timing, area, and power requirements.
• Support DFT strategy and test case development; assist with test bench debugging and simulations.
• Collaborate with analog team for AMS modeling and verification scenarios.
• Develop detailed design documents and participate in design reviews.

Skills

Verilog / SystemVerilog RTL

ASIC design methodology

Lint, CDC & RDC tools

Block-level & chip-level verification

Debug RTL & gate-level simulations

Written and verbal English

Willingness to travel

DSP concepts

Mixed-signal design methodologies

Scripting

AMBA / I2C protocols

Education

Degree in Electrical Engineering / Electronics / Computer Engineering / Computer Science or related field

Tools

Lint tools

CDC/RDC tools

P&R tooling

Job description

Renesas Electronics is seeking a highly skilled and motivated Staff Digital Design Engineer to join our growing hardware development team in Chandler, AZ. In this role, you will be responsible for designing power and area-optimized digital circuits for complex mixed-signal applications.

Job Purpose & Dimensions

• Interpret high level requirements to architect, design & integrate low‑power digital circuits for mixed‑signal data conversion and power management products in advanced process nodes.
• Support full product lifecycle from concept to mass‑production; communicating closely with wider organization through the various stages of silicon development.
• Provide technical leadership & influence to the digital design team by contributing to technical discussions & reviews, mentoring junior engineers, and supporting recruitment.
• Work closely with Analog and Verification engineers to deliver high‑quality silicon solutions.

Responsibilities

• Ensuring digital development process is state‑of‑art and achieves budget, schedule, and project deliverable goals.
• Designing digital RTL that meets timing, area, power and any adhering standards specifications.
• Integrating design at the top level and running block & top‑level simulations.
• Participate in all aspects of Mixed‑signal design flow – Micro‑architecture, Design partitioning, RTL Verilog / System Verilog Design, Generating Timing Constraints, Synthesis, Interaction with P&R Team, Timing Analysis, LINT, CDC, RDC, UPF.
• Working closely with P&R team to generate a layout that meets timing, area, and power requirements.
• Support DFT strategy and implementation, and review test case development.
• Assisting with top level test‑bench debug, and running RTL & gate level simulations.
• Working with analog and digital verification engineers to come up with complex test scenarios for pre‑silicon verification.
• Supporting analog team to develop AMS, System Verilog or Verilog‑real behavioral models.
• Developing detailed block & chip level design documents and collateral.
• Holding and participating in key design reviews and completion of various checklists.
• Perform silicon evaluation as required.
• Document device errata, develop work‑around solutions, implement engineering changes when necessary.

Qualifications

• >10 years of digital design experience in one of the following areas: wireless handheld, data conversion, and power management.
• Degree‑level qualification in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related discipline.
• Fluent in Verilog / SystemVerilog RTL for digital CMOS circuit design.
• Strong understanding of ASIC design methodology.
• Strong understanding of Lint, CDC & RDC tools.
• Strong understanding of block‑level & chip‑level verification techniques.
• Strong & proven ability to debug both RTL & gate‑level simulations.
• Mandatory competence in written and verbal English.
• Willingness to travel domestically or internationally on short notice.
• Ability to work independently and collaboratively.
• Preferred: experience with Digital Signal Processing (DSP) concepts and hardware realizations.
• Preferred: experience with methodology and flow automation using appropriate scripting.
• Preferred: experience with mixed‑signal design methodologies.
• Preferred: experience developing design constraints and hand‑off to P&R.
• Preferred: experience with STA and timing closure.
• Preferred: experience with low‑power design techniques, including clock and power gating (UPF).
• Preferred: experience with power analysis and optimization.
• Preferred: experience with advanced verification methodologies (UVM).
• Preferred: experience with industry‑standard protocols such as AMBA or I2C.

Equal Opportunity Employer

Renesas Electronics is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.

Export Controls

Renesas Electronics deals with dual‑use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.