Staff Design Verification Engineer San Jose, California, United States

Tbwa Chiat/Day Inc; California (MO); On-site; USD 140,000 - 225,000; Full time

Job summary

An established industry player is seeking a Staff Design Verification Engineer to join their dynamic team. This role involves designing and implementing innovative verification solutions for cutting-edge Open RAN SoC functional blocks. You will work closely with a talented international team, utilizing your expertise in SystemVerilog and UVM to drive verification processes. If you thrive in a fast-paced environment and enjoy taking ownership of projects, this position offers a unique opportunity to make a significant impact in the world of 5G technology. Join a company that values innovation and creativity, and be part of a team that is transforming the future of radio technology.

Benefits

Comprehensive group health plan

Matching 401(k)

Training reimbursement

Paid vacation

Paid sick leave

Paid holidays

Maternity/paternity leave

Jury leave

Pre-IPO stock options

Qualifications

• 10+ years of design verification experience with a Master's degree.
• Strong knowledge of SystemVerilog and UVM, with proficiency in Python.

Responsibilities

• Design and implement IP and SoC-level test benches for verification.
• Collaborate with architects to ensure test coverage and completeness.

Skills

SystemVerilog

UVM

SystemVerilog Assertions (SVAs)

Python

Tcl

HW/SW co-verification

debugging RTL

verification tools

Education

Master’s degree in engineering

Tools

NC Verilog

VCS

QuestaSim

Cadence verification tools

Job description

InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios continues to push the boundaries of radio technology and innovation.

As a Staff Design Verification Engineer, you will work closely with our US and India verification team to develop innovative Open RAN SoC functional blocks for 5G cellular base stations. The ideal candidate is comfortable in a fast-paced, multi-disciplinary team environment and can creatively solve complex problems.

This position offers an excellent opportunity for someone who enjoys directly impacting a smaller, dynamic team. If you prefer an environment where you can take ownership of projects and contribute significantly to the development process, this could be an ideal role for you.

Key Responsibilities

• Design and implement IP and SoC-level test benches using verification components. The test benches will support random and directed testing, including custom and off-the-shelf Verification IP (VIP) and Universal Verification Components (UVCs).
• Develop and execute verification plans aligned with design specifications.
• Collaborate with architects and designers to ensure test coverage and completeness.
• Work on HW/SW co-verification, developing and executing test cases, APIs, and debugging in hardware and software environments.
• Utilize constrained random verification, functional coverage, code coverage, and assertions for verification goals.
• Work closely with a diverse, multi-national verification team and gain exposure to modeling (TLM), HW emulation/acceleration, and software-driven verification.

Job Requirements

• Ten years of experience in design verification and a Master’s degree in engineering (or equivalent)
• Strong knowledge of SystemVerilog, UVM, and writing SystemVerilog Assertions (SVAs)
• Experience in block/chip-level verification, with familiarity in hardware/software co-verification, debugging RTL, and verification tools
• Proficiency in Python and Tcl for scripting. Familiarity with simulation tools like NC Verilog, VCS, and QuestaSim
• Energetic, self-motivated, and capable of working independently and collaboratively in a team environment

Desired Skills

• Experience in block or chip-level verification plans
• Understanding of the complete verification life cycle (test plan, testbench through coverage closure)
• Knowledge of Cadence verification tools and UVM verification methodologies
• Experience with wireless communication standards such as 3GPP, WiFi, 4G/5G, or similar technologies
• Ability to thrive in environments with changing or incomplete requirements while developing creative solutions and workarounds

Compensation and Benefits:

At InnoPhase, our compensation package includes base pay and pre-IPO stock options. The base pay range for this role is between $140K-$225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.

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