Staff CPU Formal Verification Engineer

SiFive; California (MO); On-site; USD 140,000 - 170,000; Full time

Job summary

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high‑performance CPU core functionality. You will own verification plans, develop property sets, and mentor other engineers in formal methods.

You will collaborate with architecture, RTL, and simulation DV teams to improve proof convergence and verification quality on out‑of‑order cores. You will apply formal techniques to frontend, midcore control, issue logic, and memory/order handling, shaping scalable

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 7+ years of ASIC, CPU/core, or SoC design verification with significant ownership for a Staff role.
• Direct experience with CPU/core verification and solid understanding of computer architecture and CPU microarchitecture.
• Hands-on experience with formal verification for RTL, including assertion-based verification, proof analysis, abstraction techniques, and closure of non-trivial properties.
• Experience developing assertions and formal strategies for control-heavy, ordering-sensitive, or interface-sensitive hardware behavior.
• Strong debugging skills across specification, RTL, properties, and verification infrastructure.
• Familiarity with scripting or programming in Python, Perl, Tcl, or similar languages used for automation and infrastructure.

Responsibilities

• Own formal verification planning and execution for one or more high-performance out-of-order CPU core areas, from block-level proof strategy through signoff-oriented closure.
• Develop formal verification plans based on architectural intent and microarchitectural risk, including assumptions, assertions, covers, abstraction strategy, and closure criteria.
• Create and maintain scalable formal environments, property sets, checkers, harnesses, and proof infrastructure for complex CPU control, ordering, and interface behavior.
• Target high-value CPU verification problems such as pipeline control, issue and dispatch correctness, flush and replay behavior, register/data movement correctness, load-store ordering, hazard handling, forward progress, and clock-gating correctness.
• Use the right mix of abstraction, decomposition, bounded proofs, connectivity checks, X-prop style reasoning, and bug-hunting strategies to improve proof convergence and debug efficiency.
• Analyze proof failures, counterexamples, vacuity, over-constraint, and incompleteness, and drive fixes across RTL, properties, assumptions, and verification infrastructure.
• Partner closely with architecture, RTL, and simulation-focused DV engineers to review specifications, identify ambiguities early, and align formal results with broader verification goals.
• Contribute reusable formal methodology, automation, debug workflows, and infrastructure that improve productivity and verification quality across future CPU core programs.
• Mentor other engineers through reviews, property-quality guidance, and formal-debug best practices.

Skills

Debugging skills

Ownership

Verif methodology

Python scripting

Collaboration

Mentoring

Education

Bachelor's or Master's in Electrical Engineering / Computer Engineering / Computer Science

Tools

Formal verification tooling

RTL assertions & proofs

Job description

SiFive is seeking a Staff Design Verification Engineer to drive formal verification of high‑performance CPU core functionality. You will own verification plans, develop property sets, and mentor other engineers in formal methods.

You will collaborate with architecture, RTL, and simulation DV teams to improve proof convergence and verification quality on out‑of‑order cores. You will apply formal techniques to frontend, midcore control, issue logic, and memory/order handling, shaping scalable