Staff Analog Layout Engineer

Neurophos; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

100% coverage of health plan premiums

Unlimited PTO

401(k) matching

Stock option opportunities

Customizable benefits packages

Job summary

Neurophos is seeking a Senior or Staff Analog Layout Engineer in San Jose, CA, to advance cutting-edge full-custom electronic transceivers for their innovative photonic AI platform. Applicants should have extensive experience in custom IC layout and mastery of EDA tools.

This pivotal role requires a deep understanding of deep-submicron processes and offers a unique chance to contribute to breakthrough technology at the intersection of photonics and AI.

Qualifications

• 3-8+ years of custom or block‑level IC layout experience in deep‑submicron.
• Mastery of EDA tools for layout and verification.
• Deep understanding of layout techniques and electro‑migration.

Responsibilities

• Perform IC layout execution of high-speed analog/RF circuits.
• Optimize layouts for TSMC manufacturing constraints.
• Deliver IP-level floor planning and signal distribution.

Skills

Analog layout expertise

Custom IC layout experience

Deep-submicron techniques

Industry-standard EDA tools

Education

B.S. or M.S. in Electrical or Computer Engineering

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Mentor Calibre

Siemens ICV

Job description

About Neurophos

The demand for new datacenters and AI compute is rapidly outpacing the planet’s energy capacity. Digital solutions are hitting a power wall as we approach the physical limits of traditional silicon. Conquering this bottleneck isn’t about bigger chips or more of them; it means rethinking the fundamental architecture. The industry’s current path isn’t going to meet the need, so we took a different approach.

Instead of traditional electronic circuits, we use silicon photonics and an active, programmable metasurface to perform matrix multiplications at the speed of light. Our optical cells are 10,000x smaller than traditional photonic components, enabling unprecedented density. By using photonics instead of electricity, our chips become more efficient as they scale. This architecture will deliver up to 100 times the energy efficiency of existing solutions while significantly improving performance for large-scale AI inference.

We’ve assembled a world‑class team of industry veterans and recently raised a $110M Series A led by Gates Frontier. Participants include M12 (Microsoft’s Venture Fund), Carbon Direct Capital, Aramco Ventures, Bosch Ventures, Tectonic Ventures, Space Capital, and others. We have also been recognized on the EE Times Silicon 100 list for several consecutive years.

Join us and shape the future of computing!

Position Overview

We are seeking a seasoned Senior or Staff Analog Layout Engineer to play a vital role in developing cutting‑edge full‑custom electronic transceiver components that interface directly with our custom silicon photonics and are essential to our revolutionary photonic AI platform. You will develop and optimize high‑performance Analog IPs tailored for TSMC’s deep‑submicron processes, including N12, N3P, and N2P. You will push the boundaries of Power, Performance, and Area (PPA) while mitigating the impact of Restricted Design Rules (RDRs) and electromigration.

Location

San Jose, CA or Hsinchu, Taiwan. Full‑time onsite position.

Key Responsibilities

• Perform custom IC layout execution of high‑speed analog/RF circuits.
• Optimize layout solutions to meet stringent TSMC manufacturing constraints, DFM rules, and antenna restrictions.
• Deliver IP‑level floor planning, power planning, and signal distribution, implementing layout techniques for strict ESD and latch‑up prevention.
• Execute and debug block‑level design sign‑offs, including DRC (Design Rule Check), LVS (Layout Versus Schematic), and RC extraction using standard industry tools.
• Evaluate layout trade‑offs among area, yield, and performance; implement the power and clock delivery networks to ensure power and signal integrity.
• Coordinate directly with circuit designers, CAD engineers, and EDA vendors to ensure IP design fits seamlessly into the production flow.

Qualifications

• B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a closely related discipline.
• 3-8+ years of professional custom or block‑level IC layout experience in deep‑submicron, advanced FinFET/GAA nodes (3 nm, 2 nm, etc.).
• Mastery of industry‑standard EDA tools for layout and verification (e.g., Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV).
• Deep understanding of deep‑submicron layout techniques, parasitic reduction, matching strategies, and electro‑migration (EM/IR).

Preferred Skills

• Prior tape‑out success in TSMC N3 or N2 process nodes.
• Domain knowledge in laying out high‑performance analog/mixed‑signal blocks, such as PLLs and Data Converters (ADC/DAC).
• Working knowledge of layout automation scripting languages (e.g., TCL, Perl, Python).

What We Offer

This is an opportunity to play a pivotal role in an innovative startup redefining the future of AI hardware. Work on a game‑changing technology at the intersection of photonics and AI as part of a collaborative and brilliant team. You’ll contribute to a platform that redefines computational performance and accelerates the future of artificial intelligence. Come help us bring this transformative technology to the world.

Benefits

Join a team that invests in your future and your well‑being. At Neurophos, we offer:

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO. No rigid vacation banks, just a focus on delivery.
• 401(k) matching and stock option opportunities to ensure our success is your success.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized benefits. Choose the plans that fit your life and take the cash back for those that don’t.