STA Design Engineer (Static Timing Analysis)

Advanced Micro Devices, Inc.; California, San Jose (MO, CA); On-site; USD 90,000 - 130,000; Full time

Job summary

An innovative company is on the lookout for a dynamic ASIC Design STA Engineer to join their team. In this role, you'll develop large SoCs with multiple physical blocks, ensuring high-quality designs through meticulous timing constraints and automation. Your expertise in SDC, EDA tools, and TCL scripting will be pivotal in enhancing RTL quality metrics and streamlining processes. This position offers a unique opportunity to collaborate with talented professionals in a hybrid work environment, where your contributions will directly impact cutting-edge technology advancements in computing. If you're ready to push the boundaries of technology and thrive in a collaborative atmosphere, this role is perfect for you.

Qualifications

• Extensive experience in SDC development and debugging.
• Familiarity with front-end (RTL) and back-end (Synthesis and P&R) processes.

Responsibilities

• Develop complex multi-mode/multi-corner timing constraints.
• Maintain RTL quality metrics and automate processes.
• Collaborate with CAD teams on synthesis and STA workflows.

Skills

SDC Development

EDA Tools Proficiency

TCL Scripting

RTL Quality Metrics

Analytical Skills

Problem-Solving Skills

Education

Bachelor's Degree in Electrical Engineering

Master's Degree in Computer Engineering

Tools

Synopsys Design Compiler

PrimeTime

Spyglass

Fishtail

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences—building blocks for data centers, AI, PCs, gaming, and embedded systems. Underpinning our mission is AMD's culture: we push innovation to solve important challenges, strive for execution excellence, and foster a culture of being direct, humble, collaborative, and inclusive of diverse perspectives.

THE ROLE:

AMD is seeking an ASIC Design STA engineer to develop large SoCs with multiple physical blocks and over 300 clock domains. Responsibilities include building and verifying timing constraints for complex SoC designs, requiring expertise in SDC, EDA tools, and TCL scripting. Candidates should have extensive experience in SDC development and debugging, improving RTL quality metrics, and automating processes. Familiarity with front-end (RTL) and back-end (Synthesis and P&R) processes is preferred.

THE PERSON:

High-energy candidates with strong communication skills and organized work habits will excel. Team orientation and goal focus are essential.

KEY RESPONSIBILITIES:

1. Develop complex multi-mode/multi-corner timing constraints compatible with RTL and signoff.
2. Maintain RTL quality metrics in hierarchical designs and automate these processes.
3. Implement pre-route timing checks and QoR cleanup to prevent SDC issues and ensure quality handoff.
4. Collaborate with CAD teams on synthesis and STA workflows.
5. Combine SDC expertise, EDA tool proficiency, and TCL scripting skills in both EDA environments and Linux shell scripts.
6. Review and improve processes for early issue detection during design.

PREFERRED EXPERIENCE:

• Experience with EDA tools for RTL quality checks.
• Building timing constraints for IPs, blocks, and full-chip in hierarchical flows.
• Analyzing timing reports and resolving related issues.
• Ability to multitask and learn new tools and methodologies.
• Experience with Synopsys Design Compiler, PrimeTime, Spyglass, Fishtail, etc.
• Developing complex TCL scripts in Synopsys tools.
• Creating custom TCL QC and QoR checks.
• Strong analytical and problem-solving skills.

ACADEMIC CREDENTIALS:

• Bachelor's or Master's degree in Electrical or Computer Engineering.

LOCATION:

San Jose, CA

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Benefits are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based services. We are an equal opportunity employer and consider all applicants without regard to legally protected characteristics. We encourage all qualified candidates to apply and will provide accommodations during the recruitment process.