Sr. Staff SoC RTL Engineer

Ambiq; Austin (TX); Sur place; USD 150 000 - 210 000; Plein temps

Résumé du poste

Ambiq, based in Austin, seeks a Senior Staff SoC RTL Engineer to architect and deliver digital hardware inside next‑gen ultra-low‑power MCUs/SoCs. This hands-on role spans microarchitecture through tapeout and silicon bring-up, with ownership across the full silicon lifecycle.

You'll collaborate with ARM-based CPU subsystems, AMBA interconnects, and verification teams, shaping low‑power strategies and ensuring production-quality RTL in Verilog/SystemVerilog.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of hands-on ASIC or SoC RTL design experience.
• Ownership of complex digital blocks, IPs, or subsystems.
• Experience creating or contributing to architecture and microarchitecture specifications.
• Understanding of front-end ASIC development, including synthesis, timing, LINT, CDC, and RDC.
• Experience working with verification and Physical Design teams through design closure.
• Familiarity with ARM-based SoCs, CPU subsystems, or AMBA protocols such as AHB, APB, or AXI.
• Experience supporting tapeout, silicon bring-up, or post-silicon debug.
• Ability to explain design decisions, tradeoffs, and technical risks clearly.
• Strong problem-solving skills and a willingness to remain hands-on.

Responsabilités

• Define the microarchitecture of digital SoC modules and subsystems.
• Develop production-quality RTL using Verilog and SystemVerilog.
• Own complex blocks from specification through pre-tapeout signoff.
• Integrate internal and third-party IP into MCU and SoC platforms.
• Work with ARM-based CPU subsystems and AMBA-based interconnects such as AHB, APB, or AXI.
• Partner with verification engineers on test planning, debug, and coverage closure.
• Collaborate with Physical Design teams to resolve timing, power, area, and implementation issues.
• Run, analyze, and resolve LINT, CDC, and RDC violations.
• Support FPGA prototyping, silicon bring-up, and post-silicon debug.
• Contribute to low-power design through clock gating, power management, and efficient data movement.
• Mentor less-experienced engineers and contribute to technical decisions across teams.

Connaissances

RTL design

ASIC/SoC ownership

ARM AMBA protocols

Synthesis & timing

Debug & verification coordination

Power/low-power design

Formation

Bachelor’s degree in Electrical Engineering or Computer Engineering

Outils

Verilog

SystemVerilog

Tapeout experience

AMBA interconnects

Description du poste

Ambiqis on a mission to enable intelligence everywhere — powering the AI edge revolution with the world's lowest-power semiconductor solutions.

Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.

Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology.

We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency.

At Ambiq, we live by five values:Innovate. Collaborate. Focus. Learn. Achieve.

If that's you, join us — the intelligence everywhere revolution starts here.

Help Build the Digital Hardware Behind Ultra-Low-Power Edge Intelligence

Ambiq is on a mission to enable intelligence everywhere by delivering some of the world’s most energy-efficient semiconductor solutions.

Our ultra-low-power MCUs and SoCs power smart wearables, medical devices, connected sensors, and intelligent edge products where performance matters—but every microwatt counts.

We are looking for a Senior Staff SoC RTL Engineer to help architect, design, and deliver the digital hardware inside our next-generation products.

This is a hands-on individual contributor role for an experienced RTL engineer who wants meaningful ownership across the full silicon lifecycle—from microarchitecture and RTL development through design closure, tapeout, and silicon bring-up.

What You’ll Do

• Define the microarchitecture of digital SoC modules and subsystems
• Develop production-quality RTL using Verilog and SystemVerilog
• Own complex blocks from specification through pre-tapeout signoff
• Integrate internal and third-party IP into MCU and SoC platforms
• Work with ARM-based CPU subsystems and AMBA-based interconnects such as AHB, APB, or AXI
• Partner with verification engineers on test planning, debug, and coverage closure
• Collaborate with Physical Design teams to resolve timing, power, area, and implementation issues
• Run, analyze, and resolve LINT, CDC, and RDC violations
• Support FPGA prototyping, silicon bring-up, and post-silicon debug
• Contribute to low-power design through clock gating, power management, and efficient data movement
• Mentor less-experienced engineers and contribute to technical decisions across teams

What We’re Looking For

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 8+ years of hands-on ASIC or SoC RTL design experience
• Demonstrated ownership of complex digital blocks, IPs, or subsystems
• Experience creating or contributing to architecture and microarchitecture specifications
• Understanding of front-end ASIC development, including synthesis, timing, LINT, CDC, and RDC
• Experience working with verification and Physical Design teams through design closure
• Familiarity with ARM-based SoCs, CPU subsystems, or AMBA protocols such as AHB, APB, or AXI
• Experience supporting tapeout, silicon bring-up, or post-silicon debug
• Ability to explain design decisions, tradeoffs, and technical risks clearly
• Strong problem-solving skills and a willingness to remain hands-on

Experience That Would Be Especially Valuable

• ARM Cortex-M or embedded CPU subsystem integration
• MCU architecture and peripheral integration
• AMBA interconnect, memory maps, DMA, interrupt controllers, or bus arbitration
• Low-power SoC design, including UPF, power gating, clock gating, retention, or multi-voltage domains
• Memory controllers, DSPs, hardware accelerators, security blocks, or AI-related IP
• FPGA prototyping or emulation
• Third-party IP evaluation and integration
• Multiple successful production tapeouts

Why Ambiq?

At Ambiq, you will not disappear into one narrow corner of a massive organization.

You will have the opportunity to:

• Own meaningful portions of real products
• Work across the full silicon lifecycle
• Collaborate directly with senior technical leaders
• See your work ship in high-volume customer products
• Help solve some of the hardest power and performance challenges in edge computing

This role is based at Ambiq’s Austin headquarters and requires working onsite five days per week. Candidates must be currently authorized to work in the United States.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Ambiq Micro, Inc.’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.