Sr. Staff High-Speed Communication Architect – AI Systems

Tenstorrent; Jackson (TN); Híbrido; USD 100.000 - 500.000; Jornada completa

Descripción de la vacante

Tenstorrent seeks an exceptional Senior Staff or Principal High-Speed Communication Architect to define the next generation of high-bandwidth architectures for rack-scale AI accelerator systems.

This role owns the end-to-end communication path between AI chips, GPUs, CPUs, switches, memory systems, and network interfaces, spanning 224G+ electrical links, flyover cables, near-package and co-packaged optics, and rack-scale fabrics.

Formación

• 15+ years of experience in high-speed electrical or optical communications.
• Expert in 112G, 224G SerDes, PAM4 signaling, link budgets, FEC.
• Hands-on with 224G-class channels, flyover cables, near-package optics.

Responsabilidades

• Define scalable rack-scale comm architecture for AI accelerators, GPUs, CPUs, switches, and I/O.
• Own end-to-end electrical and optical channel architecture from die to fiber.
• Lead 224G+ SerDes and SI architecture; set budgets for reach, loss, jitter, BER, FEC.
• Co-design interfaces with internal teams and suppliers; guide material choices and integration.

Conocimientos

High-speed systems design

Signal integrity

System-level architecture

Leadership across teams

Electrical/optical interconnects

Educación

BS/MS/PhD in EE/CE or related field

Herramientas

SerDes simulation tools

PCB/packaging design tools

Descripción del empleo

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are seeking an exceptional Senior Staff or Principal High-Speed Communication Architect to define the next generation of high-bandwidth communication architecture for rack-scale AI accelerator systems. This role owns the end-to-end communication path between AI chips, GPUs, CPUs, switches, memory systems, and network interfaces, spanning 224G+ electrical links, flyover cables, near-package and co-packaged optics, and rack-scale fabrics. You will make system-level tradeoffs across architecture, ASIC and package design, PCB, connectors and cables, signal integrity, optical technology, and rack mechanics.

This role is hybrid, based out of North America.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You hold a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, and have 15+ years of experience in high-speed electrical or optical communications.
• You have architected systems using 112G, 224G, or higher-rate SerDes and bring deep knowledge of PAM4 signaling, channel behavior, link budgets, equalization, jitter, BER, and FEC.
• You have hands-on experience with 224G-class electrical channels, flyover cable technology, and near-package optics, optical engines, or similarly dense optical interconnects.
• You are an expert in signal integrity and high-speed package, PCB, connector, cable, and optical link design, with experience modeling channels and correlating simulation results with lab measurements.
• You can lead architecture decisions across ASIC, package, PCB, optical, mechanical, and system teams, balancing bandwidth, reach, power, latency, cost, thermal impact, manufacturability, and reliability.

What We Need

• Define scalable rack-scale communication architecture for AI accelerators, GPUs, CPUs, switches, network adapters, memory, and I/O, including topology, lane counts, link budgets, redundancy, and 224G, 448G, and future-rate interfaces.
• Own end-to-end electrical and optical channel architecture, from die and package through PCB, connectors, flyover cables, optical engines, and fiber, and determine where to use on-package, board-level, flyover, near-package, or co-packaged interconnects.
• Lead 224G+ SerDes and signal-integrity architecture: set channel reach and loss limits; model insertion/return loss, crosstalk, reflections, vias, jitter, and equalization; and establish electrical and optical power, latency, BER, FEC, and thermal budgets.
• Co-design package, PCB, connector, cable, and optical interfaces with internal teams and suppliers; guide low-loss materials, routing, breakout, cable and fiber attach, optical-engine placement, and integration into dense rack and high-power accelerator systems.
• Drive simulation and validation from architecture through production readiness, including reusable modeling methods, SI simulation correlation, 224G+ lab test plans, measurement and failure analysis, supplier requirements, technology roadmaps, and cross-functional design reviews.

What You Will Learn

• How to define the complete communication fabric for next-generation rack-scale AI systems as bandwidth scales from 224G to 448G and beyond.
• How to make system-level choices between electrical reach, flyover cables, near-package optics, and co-packaged optics while balancing power, latency, cost, volume, and reliability.
• How package, PCB, connector, cable, optical-engine, and fiber decisions combine to determine end-to-end channel performance and manufacturability.
• How to shape the interconnect technology roadmap through collaboration with ASIC, package, PCB, optical, mechanical, and system teams, as well as semiconductor and component suppliers.
• How to evaluate and bring emerging technologies, including silicon photonics, 800G/1.6T+ optics, advanced packaging, and next-generation SerDes, toward production AI infrastructure.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstortex offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.