Sr Staff Applications Engineer, HAV Solutions

Synopsys; Mountain View (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys is seeking a senior Hardware‑Assisted Verification expert to lead deployments of HAPS-200 and ProtoCompiler for strategic customers building billion‑gate SoCs across AI, automotive, hyperscaler, and aerospace segments.

You will drive the full ASIC‑to‑FPGA flow, debug complex interfaces, mentor engineers globally, and influence roadmaps by translating customer needs into practical verification solutions in production environments.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands‑on experience.
• 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation.
• Deep expertise in FPGA synthesis, place-and-route, multi‑FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools.
• Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture.
• Hands‑on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high‑speed SerDes protocols.
• Proficiency in Tcl, Python, or shell scripting for automation and flow development.
• Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms.

Responsibilities

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments.
• Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems.
• Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures.
• Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures.
• Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning.
• Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation.
• Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums.

Skills

FPGA implementation

ASIC design

ASIC verification

FPGA prototyping

emulation

SystemVerilog

UVM

assertions

functional coverage

verification testbench

Tcl scripting

Python scripting

shell scripting

debug instrumentation

ProtoCompiler

HAPS-200

multi-FPGA flow

Education

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

Xilinx Vivado

Intel Quartus

Synopsys HAPS

ProtoCompiler

ZeBu

Palladium

Protium

Veloce

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years moving between RTL, FPGAs, and real hardware, and you know that the gap between a design that compiles and one that actually boots is where most projects stall. You understand partitioning tradeoffs, clock domain crossings, and why a PCIe link trains in simulation but fails on the board. You have debugged DDR timing issues at 2 a.m., explained why a billion-gate SoC will not fit without rearchitecture, and walked a customer through a critical bring-up when everything seemed broken.

You do not just run tools. You understand what ProtoCompiler is doing under the hood, why timing closed on FPGA A but not FPGA B, and how to instrument a design for visibility without destroying performance. When a customer escalation lands, you are the person who can reproduce it, explain it to R&D, and propose a workaround that actually works in production.

You have worked with hyperscalers, automotive teams, AI chip startups, or aerospace groups building systems too complex to simulate. You speak their language. You know the difference between emulation and prototyping, and you can articulate when each makes sense without sounding like a sales pitch. At Synopsys, you will work on the hardest prototyping problems in the industry with customers who are building the next generation of AI, automotive, and datacenter silicon.

What You'll Be Doing

• Lead technical deployments of HAPS-200 and ProtoCompiler for strategic customers building billion-gate SoCs across AI/ML, automotive, hyperscaler, and aerospace segments
• Drive the full ASIC-to-FPGA flow including partitioning, clock conversion, synthesis, place-and-route, timing closure, bitstream generation, and hardware bring-up on multi-FPGA systems
• Debug complex interface IP subsystems including DDR4/DDR5, LPDDR5/6/7, HBM, PCIe Gen3-6, CXL, UCIe, Ethernet, USB, AXI, and high-speed SerDes architectures
• Reproduce, analyze, and resolve critical customer escalations involving RTL issues, partitioning failures, timing violations, protocol mismatches, and hardware bring-up failures
• Collaborate directly with ProtoCompiler R&D and Product Management to validate new features, influence roadmap priorities, and represent customer requirements in product planning
• Develop and document reusable methodologies for partitioning strategies, clock architecture, debug instrumentation, verification environment adaptation, and hardware/software co-validation
• Mentor applications engineers globally, lead technical workshops and architecture reviews, and represent Synopsys at customer sites, conferences, and industry forums

The Impact You Will Have

• Enable customers to prototype and validate complex SoCs months earlier by solving partitioning, timing, and bring-up challenges that would otherwise block hardware availability
• Influence the ProtoCompiler roadmap and feature set based on direct engagement with the most demanding semiconductor and systems customers in the world
• Reduce critical customer escalations by building repeatable debug methodologies and training global teams on advanced troubleshooting techniques
• Accelerate adoption of HAPS prototyping platforms across AI accelerator, automotive SoC, and hyperscaler chip development programs
• Shape how Synopsys supports multi-die, chiplet, and UCIe-based architectures as the industry moves beyond monolithic SoCs
• Build long-term technical relationships with engineering leaders at strategic accounts, becoming the trusted advisor they call when deployments get hard
• Drive competitive wins by demonstrating technical depth in FPGA prototyping, emulation tradeoffs, and verification methodology that competitors cannot match

What You'll Need

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent hands‑on experience
• 10+ years working in FPGA implementation, ASIC design, ASIC verification, hardware-assisted verification, FPGA prototyping, or emulation
• Deep expertise in FPGA synthesis, place-and-route, multi‑FPGA partitioning, timing closure, and constraint development using Xilinx Vivado, Intel Quartus, or equivalent tools
• Strong working knowledge of SystemVerilog, UVM, assertions, functional coverage, and verification testbench architecture
• Hands‑on experience with interface IP including PCIe, DDR4/DDR5, LPDDR, Ethernet, USB, AXI, CXL, or high‑speed SerDes protocols
• Proficiency in Tcl, Python, or shell scripting for automation and flow development
• Direct experience with Synopsys HAPS and ProtoCompiler is a strong plus, as is experience with ZeBu, Palladium, Protium, or Veloce emulation platforms

Who You're

• You can walk into a room with a customer's architecture team, understand their SoC in an hour, and identify the three partitioning decisions that will make or break their prototype schedule
• When a PCIe link will not train or a DDR interface fails calibration, you know where to look first and how to instrument the design to prove your hypothesis
• You are comfortable presenting technical tradeoffs to VPs and engineering directors without oversimplifying the problem or losing the nuance that matters
• You do not wait for perfect information or complete documentation. You dig into logs, RTL, netlists, and hardware captures to figure out what is actually happening
• You have debugged designs using Verdi, runtime instrumentation, protocol analyzers, or assertion-based techniques and can teach others how to do the same
• You can explain why emulation and prototyping solve different problems, and you have the technical depth to back up that explanation with real architectural tradeoffs

The Team You'll Be Part Of

You will join the Hardware‑Assisted Verification (HAV) organization, working closely with Applications Engineers, R&D, Product Management, Sales, and Customer Success teams globally. This is a highly visible role supporting strategic semiconductor, hyperscaler, AI/ML, automotive, and aerospace customers deploying HAPS‑200, ProtoCompiler, and the broader Synopsys verification ecosystem. You will collaborate across organizations to drive customer success, influence product direction, and lead technical initiatives that shape how the industry approaches FPGA-based prototyping.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job‑related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.