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Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation for high‑performance SoCs on GF 12LP. You will own FinFET design challenges, drive PPA improvements, and push timing closure for robust performance.
The role requires hands‑on experience with Synopsys Fusion Compiler and PrimeTime, plus scripting in Tcl or Python. Remote work in the USA is supported with a comprehensive benefits package.
Full-time: Salary + Benefits + Bonuses / Contractor
Location: Remote, anywhere in USA
We are seeking a Senior Physical Design Engineer to lead the RTL-to-GDSII implementation of high-performance SoCs. In this role, you will take ownership of advanced FinFET design challenges, push Power, Performance, and Area (PPA) boundaries, and drive robust timing closure targeting the GlobalFoundries 12LP node.
The anticipated annual base salary for this position is between $135,000 to $165,000, which also includes a comprehensive benefits package.
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/