Sr. Manager, Foundation IP (Standard Cells & Memories),, Annapurna Labs

Annapurna Labs; Austin (TX); On-site; USD 241,000 - 326,000; Full time

Job summary

Annapurna Labs in Los Angeles area is seeking a Sr. Manager, Foundation IP to own the foundation IP layer end to end for Trainium and Inferentia blocks. You will lead a hands-on team, set strategy with vendors, and partner with Architecture, Physical Design, CAD and Product Engineering to achieve measurable PPA improvements.

This player‑coach role requires reviewing schematics and layouts directly, mentoring a small team, and driving a world‑class IP portfolio for next‑gen ML accelerators.

Qualifications

• BS in Electrical or Computer Engineering is required.
• Advanced degrees listed (MS or PhD) with relevant experience preferred.
• Experience as the technical interface to IP vendors or foundries and driving SOWs.

Responsibilities

• Own the foundation IP roadmap across standard cells, memory and macros.
• Define deliverable specs, negotiate SOWs, drive ECOs and release cadence.
• Influence vendor roadmaps to secure differentiating PPA features.
• Build IP intake, QA, checklists, regressions, acceptance criteria.
• Lead evaluation of libraries and memory architectures using synthesis/placement tools.
• Drive cell-architecture decisions and coordinate RTL-to-GDSII flow.
• Define memory requirements for ML accelerator workloads and Vmin targets.
• Own memory/vendor relationships and integration support for PD and DFT.

Skills

People management

Foundation IP interface

Vendor management

RTL-to-GDSII flow

Characterization strategy

PPA optimization

Scripting (Python/Tcl)

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

PhD in Electrical Engineering or related field

Tools

Synopsys PrimeLib/SiliconSmart

Cadence Liberate

Cadence Virtuoso

Synopsys ICV

HSPICE/PrimeSim

Job description

Description

Annapurna Labs, our silicon organization within AWS Utility Computing, builds the custom chips behind AWS — Graviton, Nitro, Inferentia and Trainium. Our Machine Learning Acceleration (MLA) team develops the Trainium and Inferentia SoCs that train and serve frontier AI models at datacenter scale.

Annapurna Labs, our silicon organization within AWS Utility Computing, builds the custom chips behind AWS — Graviton, Nitro, Inferentia and Trainium. Our Machine Learning Acceleration (MLA) team develops the Trainium and Inferentia SoCs that train and serve frontier AI models at datacenter scale.

On AI silicon, foundation IP is not a commodity. SRAM and register files dominate die area and power, and every picosecond and square micron in a standard cell library compounds across billions of instances. We are looking for a Sr. Manager, Foundation IP to own that layer end to end — from foundry DTCO and vendor roadmaps, through custom cell and memory definition, to characterization and silicon correlation on leading-edge GAA nodes (N3, N2 and below).

You will be the single technical point of contact for our foundation IP vendors and memory providers, lead a hands‑on team of 3–6 engineers, and partner with Architecture, Physical Design, CAD, DFT and Product Engineering to turn IP decisions into measurable PPA wins on every Trainium and Inferentia generation. This is a player‑coach role: you will set strategy and hold vendors to Amazon’s bar — and you will also review schematics, layouts and Liberty data yourself.

Key job responsibilities

• Own the foundation IP roadmap — standard cell libraries, memory compilers, custom macros, GPIO/ESD, eFuse/OTP and PVT sensors — aligned to multi‑generation Trainium and Inferentia product plans.
• Serve as the primary technical interface to foundation IP vendors and the foundry: define deliverable specifications, negotiate SOWs and schedules, and drive ECOs, version control and release cadence.
• Influence vendor roadmaps to secure features and PPA that differentiate AWS silicon; resolve quality escapes with data, not escalation alone.
• Build IP intake and QA mechanisms — checklists, regressions and acceptance criteria for every library, memory and view drop.
• Lead quantitative evaluation of competing libraries, memory compilers and cell architectures using block‑level synthesis and place‑and‑route benchmarks (Synopsys Fusion Compiler, Cadence Innovus) on representative ML datapath, SRAM‑heavy and high‑utilization blocks.
• Drive cell‑architecture decisions — cell height, mixed‑height (short/tall) libraries, VT and channel‑length flavors, nanosheet width options, backside power delivery — with clear PPA, cost and schedule tradeoffs.
• Partner with Physical Design and CAD to deploy selected IP into the RTL‑to‑GDSII flow and close the loop on post‑implementation PPA.
• Define memory requirements for ML accelerator workloads — single/dual‑port SRAM, multi‑port register files, ROM, TCAM/CAM — including capacity, banking, bandwidth, latency, Vmin and leakage targets.
• Specify bitcell selection (high‑density vs. high‑current), read/write assist, redundancy and repair, MBIST/BISR interfaces, power‑gating, retention and sleep modes.
• Own the memory vendor relationship, compiler release qualification, and integration support for Physical Design and DFT teams.
• Lead design and integration of latch‑based arrays and custom register files for small, high‑bandwidth buffers where compiler SRAM or flop arrays fall short on PPA.
• Define the selection methodology across compiler SRAM, custom macros, latch arrays and flop‑based storage; own the timing, DFT and characterization strategy for latch‑based structures.
• Drive custom macro development (multi‑port register files, TCAM/CAM) from specification through layout, characterization and silicon validation.
• Mine synthesized ML netlists and cell‑usage statistics to find custom cell opportunities — combo/complex cells, multi‑bit flops, datapath compressors and MAC‑optimized cells, ganged buffers, clock and power‑management cells.
• Write cell specifications and work hands‑on with circuit and layout engineers on topology, sizing, pin access, routability and DFM.
• Take custom cells through characterization, view generation, QA and PnR enablement, and quantify the block‑level PPA benefit.
• Own characterization strategy and quality for all foundation IP: Liberty (NLDM, CCS, ECSM), LVF/POCV, CCS noise and power, EM limits, LEF/abstracts and Verilog models.
• Set PVT corner strategy, including low‑voltage and overdrive corners, with Physical Design, signoff and Product Engineering.
• Drive characterization flows (Synopsys PrimeLib/SiliconSmart, Cadence Liberate) and view QA (e.g., Siemens Solido Crosscheck), with SPICE correlation in Synopsys PrimeSim/HSPICE and Cadence Spectre.
• Engage the foundry from early PDK versions on DTCO, cell architecture, design rules and device options for N3, N2 and below nodes.
• Work with others to define silicon characterization plans for libraries and memories (Vmin, speed, leakage, aging, self‑heating) and correlate silicon to models, on both testchips and/or products.
• Track device and reliability model updates across PDK revisions and assess their impact on IP and product PPA.
• Hire, develop and lead a small team to deliver on the above; set technical direction, review designs, and raise the bar on quality and execution.
• Report IP health, risks and PPA metrics to senior leadership through clear, data‑driven narratives and decision documents.

Basic Qualifications

• 3+ years of people management, managing engineers experience
• BS in Electrical or Computer Engineering with 12+ years, MS with 10+ years, or PhD with 7+ years of experience in standard cell, memory or custom digital circuit design
• Hands‑on transistor‑level design experience across standard cells, sequentials/latches, and SRAM or register files in FinFET or GAA technologies at 5nm or below
• Experience as the technical interface to foundation IP vendors or foundries — specifying deliverables and driving SOWs, schedules, ECOs and IP quality
• Experience evaluating standard cell library and memory PPA using block‑level synthesis and place‑and‑route
• Experience with standard cell and memory characterization and EDA views (Liberty/LVF, LEF, Verilog) using Synopsys PrimeLib/SiliconSmart or Cadence Liberate
• Proficiency with custom design and verification tools: Cadence Virtuoso or Synopsys Custom Compiler; Spectre or HSPICE/PrimeSim; Siemens Calibre or Synopsys ICV
• Scripting experience in Python, Tcl, Perl or SKILL

Preferred Qualifications

• Master's degree or Ph.D. degree in Electrical Engineering or related field
• Experience on N3, N2 or below technologies, including backside power delivery and mixed‑height standard cell libraries
• Design or integration of latch‑based arrays, custom multi‑port register files, or TCAM/CAM for high‑performance processors or ML accelerators
• Track record defining custom and combo cells (multi‑bit flops, complex/fused cells, datapath compressors) from netlist analytics, with measured block‑level PPA gains
• Memory design depth: bitcell options, read/write assist, Vmin, redundancy/repair, MBIST/BISR, low‑power modes, and memory EM/IR analysis (Ansys Totem, Cadence Voltus‑XFi)
• Test chip definition, silicon characterization and model‑to‑silicon correlation, including aging, self‑heating and EM reliability
• GPIO, ESD, eFuse/OTP and on‑die PVT sensor IP selection and integration
• Working knowledge of physical design and signoff flows: Fusion Compiler, Innovus, PrimeTime, Tempus, StarRC, Quantus, RedHawk‑SC
• Experience on AI/ML accelerator or high‑performance SoC programs taken to high‑volume production
• Demonstrated ability to influence external partners and make high‑judgment tradeoffs under ambiguity
• Demonstrated alignment with Amazon’s Leadership Principles at the Sr. Manager bar
• Functional and technical depth consistent with the scope and complexity of this role

Amazon is an equal opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.

Los Angeles County applicants: Job duties for this position include: work safely and cooperatively with other employees, supervisors, and staff; adhere to standards of excellence despite stressful conditions; communicate effectively and respectfully with employees, supervisors, and staff to ensure exceptional customer service; and follow all federal, state, and local laws and Company policies. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness and professionalism, and safeguard business operations and the Company’s reputation. Pursuant to the Los Angeles County Fair Chance Ordinance, we will consider for employment qualified applicants with arrest and conviction records.

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The base salary range for this position is listed below. Your Amazon package will include sign‑on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.

USA, CA, Cupertino - 277,400.00 - 350,000.00 USD annually

USA, TX, Austin - 241,200.00 - 325,600.00 USD annually

Company

Annapurna Labs (U.S.) Inc.

Job ID: A10586245