Sr. Engineer, Package Design California, Santa Clara

SiTime Corp.; Santa Clara (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

401k plan

Health and wellness benefits

Equity grants

Parental leave

Time off plans

Job summary

SiTime Corp. in Santa Clara, CA seeks a Senior Semiconductor Package Engineer to lead the specification, design, development and qualification of custom packaging for MEMS timing products.

You will work with OSATs and internal teams to deliver reliable, manufacturable packages, including QFN, WLCSP, ceramic, and substrate-based modules. Ideal candidates have a MS/PhD in Mechanical Engineering or Materials Science, 5+ years in semiconductor IC packaging, and hands-on CAD experience.

Qualifications

• Requires MS/PhD in Mechanical Engineering or Materials Science.
• 5+ years in semiconductor IC packaging technology.
• Experience managing overseas OSATs to bring products into production.
• Knowledge of leadframe-based, flip-chip, and substrate-based packages.
• Experience with flip-chip and bumping technologies.
• Understanding of thermal, stress, and electrical considerations in package design.

Responsibilities

• Develop new packaging technology for SiTime’s MEMS-based timing solutions.
• Lead activities for package design, development, and release-to-production.
• Develop, manage, and analyze DoEs running locally and overseas.
• Work with OSATs to prototype and test new custom package designs.
• Ensure new technologies achieve required performance, reliability, and quality requirements.
• Lead troubleshooting activities related to package design or performance.

Skills

Semiconductor packaging knowledge

OSAT management

Thermal/electrical modeling

Flip-chip and bumping knowledge

Leadframe-based/package design

English communication

Education

MS or PhD in Mechanical Engineering or Materials Science

Tools

AutoCAD

Job description

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

The Senior Semiconductor Package Engineer is responsible for the specification, design, development, and qualification of unique custom packaging technology for SiTime’s revolutionary MEMS-based timing products. Packaging technologies include QFN, WLCSP, ceramic, substrate-based, and multi-chip/package modules, all of which incorporate custom-designed MEMS and CMOS components. We value diverse experiences, perspectives, and career paths, and welcome candidates who are excited to contribute to our mission.

Responsibilities:

• Develop new packaging technology for SiTime’s MEMS-based timing solutions
• Lead activities for package design, development, and release-to-production
• Develop, manage, and analyze DoEs running locally and overseas
• Work with OSATs to prototype and test new custom package designs
• Ensure new technologies achieve required performance, reliability, and quality requirements
• Lead troubleshooting activities related to package design or performance

Qualifications & Requirements:

• M.S or PhD. Degree in Mechanical Engineering, Material Science, or other relevant field
• 5+ years’ experience in semiconductor IC packaging technology and methodology
• Experience managing overseas OSATs to bring products into production
• Knowledge of leadframe-based, flip-chip, and substrate-based packages
• Experience with flip-chip and bumping technologies
• Understanding of thermal, stress, and electrical considerations in package design
• Hands-on experience with CAD software (AutoCAD preferred but not required)
• The desire to work in a fast-paced, challenging, and risk-taking environment

Desired Characteristics & Attributes:

• Understanding of thermal, mechanical, and electrical modeling for semiconductor packages
• Understanding of material characterization techniques (DMA, TMA, TGA, etc.)
• It is not necessary to meet all job requirements to be a qualified candidate for the position.
• English proficiency is required, including the ability to effectively communicate, collaborate, and perform job responsibilities in a professional business environment.

Compensation:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans.

SiTime is an Equal Opportunity Employer . We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program.

Learn More about SiTime:

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.