Sr DFT Engineer ( 100% Remote)

Encore Semi, Inc.; Austin (TX); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days

Holidays 10

Medical benefits 80%

Dental & Vision 50%

Life Insurance & Disability

Tuition reimbursement

401k Traditional & Roth

EAP

Job summary

Encore Semi, Inc. seeks a Senior DFT Engineer to lead test architecture for complex SoCs, working from RTL to silicon bring-up. This 100% remote role supports collaboration with design and verification teams across the United States.

The ideal candidate has 8+ years in ASIC DFT, IJTAG (IEEE 1687) with ICL/PDL, and strong experience in Tessent, Xcelium, VCS, or QuestaSim. BS/MS in EE/CE is required.

Qualifications

• 8+ years of proven industry experience in ASIC DFT engineering.
• IEEE 1687 IJTAG architecture experience with ICL and PDL formats.
• Mentor Tessent tool suite proficiency.

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

Verilog/SystemVerilog

Tcl scripting

Python scripting

Perl scripting

Education

BS or MS in Electrical/Computer Engineering

Tools

Tessent (Mentor Graphics)

Xcelium

VCS

QuestaSim

Job description

Sr DFT Engineer - 100% remote

Full-time: Salary + Benefits + Bonuses / Contractor

Work Status: US Citizen OR GC holder required.

Location: Remote, anywhere in USA

We are seeking an experienced Senior DFT Engineer to lead test architecture and implementation for complex SoCs. You will work closely with design and verification teams to drive DFT requirements from RTL through to silicon bring-up, ensuring the highest quality test coverage.

Key Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-generation ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Required Qualifications

• Experience: 8+ years of proven industry experience in ASIC DFT engineering.
• IJTAG: Strong hands-on expertise with IEEE 1687 (IJTAG) architecture, specifically utilizing ICL and PDL formats.
• DFT Tools: Deep proficiency with the Mentor Graphics (Siemens) Tessent tool suite.
• Simulation: Solid simulation, verification, and debug skills using Xcelium, VCS, or QuestaSim.
• Core Skills: Fluency in Verilog/SystemVerilog and strong scripting abilities (Tcl, Python, or Perl).

Education: BS or MS in Electrical Engineering, Computer Engineering, or a related field.

The anticipated annual base salary for this position is between $135,000 to $150,000, which also includes a comprehensive benefits package.

Full-Time Benefits

• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&DD and Long-Term Disability
• Tuition reimbursement

Equal Opportunity Policy Statement

Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.

Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.

LinkedIn :: https://www.linkedin.com/in/rtl2gds/