Design Verification Engineer, Infinity Fabric and Chiplet Interconnect

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

AMD in Santa Clara seeks a Design Verification Engineer to verify Infinity Fabric transport-layer features and cross-die connectivity across Client, Server, Graphics, and Semi-Custom products.

You will collaborate with architecture, RTL, firmware, and verification teams to solve complex challenges, strengthen verification methodologies, and deliver high-quality silicon across AMD’s portfolio. This role emphasizes rigorous debugging and scalable verification environments.

Qualifications

• Proficiency in IP-level ASIC verification.
• Experience debugging firmware and RTL using simulation and debugging tools.
• Hands-on experience with UVM concepts, testbenches, and SystemVerilog.
• Experience developing UVM-based verification frameworks, testbenches, processes, and flows.
• Experience with Verilog, SystemVerilog, C, and C++.

Responsibilities

• Define and execute verification strategies for Infinity Fabric features and subsystems with cross-project impact.
• Partner with architectures, RTL designers, firmware engineers to influence feature verification.
• Own verification planning and execution for critical areas, identify risks and mitigations.
• Develop robust verification environments and methodologies including directed and constrained-random testing with SystemVerilog and UVM.
• Debug complex interactions across testbenches, RTL, firmware, and architectural models.
• Drive verification methodologies and infrastructure improvements for efficiency.
• Analyze functional and code coverage and drive coverage closure strategies.
• Collaborate across teams to align verification activities and dependencies.
• Share knowledge and support the broader engineering team.

Skills

IP-level ASIC verification

Firmware/RTL debugging

UVM concepts

SystemVerilog

Verilog

C/C++

Debugging across testbenches

Education

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

THE ROLE:

The Infinity Fabric transport layer verification team is looking for a Design Verification Engineer to help verify the advanced interconnect technology at the heart of AMD’s products.

In this role, you will work on configurable switches, transport-layer features, and die-to-die connectivity used across Client, Server, Graphics, and Semi-Custom products. You will collaborate with architecture, RTL design, firmware, and verification teams to solve complex technical challenges, strengthen verification methodologies, and help deliver high-quality silicon across AMD’s product portfolio.

THE PERSON:

You are passionate about processor architecture, digital design, and verification. You enjoy solving challenging technical problems, debugging complex behavior, and learning how interconnected systems work.

You are a collaborative team member with strong analytical, problem-solving, and communication skills. You work effectively with engineers across disciplines, locations, and time zones, and you are comfortable taking ownership of problems and driving them through resolution.

KEY RESPONSIBILITIES:

• Define and execute verification strategies for complex Infinity Fabric features and subsystems with cross-project and cross-product impact
• Partner with architects, RTL designers, firmware engineers, and verification teams to influence feature definition, implementation, and verification readiness throughout the design cycle
• Own verification planning and execution for technically critical areas, including identifying risks, evaluating trade-offs, and developing mitigation strategies
• Develop robust, scalable verification environments and methodologies, including directed and constrained-random testing using SystemVerilog and UVM
• Debug complex interactions across testbenches, RTL, firmware, and architectural models and drive issues through resolution
• Solve complex and ambiguous verification challenges by developing new approaches or extending existing methodologies, processes, and infrastructure
• Analyze functional and code coverage and drive coverage closure strategies that balance quality, schedule, and compute efficiency
• Drive improvements to verification processes, tools, automation, and workflows that increase productivity, quality, and execution efficiency
• Collaborate across teams and programs to align verification activities, technical dependencies, and shared objectives
• Share technical knowledge, contribute to verification best practices, and support the technical development of the broader engineering team

PREFERRED EXPERIENCE:

• Proficiency in IP-level ASIC verification
• Experience debugging firmware and RTL using simulation and debugging tools
• Hands-on experience with UVM concepts, testbenches, and SystemVerilog
• Experience developing UVM-based verification frameworks, testbenches, processes, and flows
• Experience with Verilog, SystemVerilog, C, and C++
• Experience developing directed and constrained-random verification environments
• Experience with functional and code coverage analysis and coverage closure
• Experience automating verification workflows in distributed compute environments
• Exposure to simulation profiling, performance and efficiency improvements, acceleration, and HLS tools and processes
• Working knowledge of SystemC and TLM, with related hands-on experience
• Scripting experience with Perl, Ruby, Makefiles, shell, or similar languages
• Experience working with complex, highly configurable digital designs and subsystems
• Experience working in Linux and Windows environments
• Strong debugging, analytical, and problem-solving skills

ACADEMIC CREDENTIALS:

• BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science preferred.

LOCATION:

Santa Clara, CA

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's Responsible AI Policy is available here.

This posting is for an existing vacancy.