Sr. Coherent Interconnect Micro-architect/Logic Designer

Samsung Electronics America; Austin (TX); Hybrid; USD 174,000 - 306,000; Full time

Job summary

Join a forward-thinking company where you can lead the micro-architecture development of cutting-edge coherent interconnect technologies. This exciting role involves collaborating with diverse teams to design high-performance computing solutions that impact millions globally. You'll engage in architectural exploration, drive RTL design, and mentor junior engineers in a dynamic environment. With a commitment to innovation and excellence, this role offers the chance to shape the future of semiconductor technology while enjoying a supportive and collaborative workplace culture. If you're passionate about pushing the boundaries of technology, this opportunity is perfect for you.

Benefits

Medical Insurance

Dental Insurance

Vision Insurance

401(k)

Free Onsite Lunch

Tuition Assistance

Paid Time Off

Wellness Incentives

Employee Purchase Program

MBO Bonus Compensation

Qualifications

• 15+ years experience in RTL design for high-performance digital designs.
• Strong background in microarchitecture and ASIC design flow.
• Ability to mentor junior engineers and collaborate effectively.

Responsibilities

• Lead micro-architecture development of custom coherent interconnect IP.
• Collaborate with architects to define next-generation interconnects.
• Produce quality RTL on schedule while meeting performance goals.

Skills

Verilog

RTL Design

Microarchitecture Development

ASIC Design Flow

Communication Skills

Mentoring

Power Optimization

System Caches Knowledge

Scripting (Perl/Python)

Education

Bachelor’s degree in Computer Science/Computer Engineering

Master’s degree

PhD

Tools

Verilog/VHDL

STA

ECO

Job description

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Senior Coherent Interconnect Micro-Architect, you will be responsible for leading the micro-architecture development of custom coherent interconnect IP and/or last level cache blocks. In this role you will be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning and driving the critical coherent interconnect related RTL design, performance and power optimization and also work on logic debug and timing closure of the design. Solid engineer foundation and RTL design experience are desired for success.

• You drive the timely development of custom coherent interconnect IP and/or last level cache [LLC] blocks.
• You engage with the architects and help define next-generation Samsung coherent interconnects and LLC.
• You perform microarchitecture development and specification - from early high-level architectural exploration through micro architectural research and arriving at a detailed specification.
• You work with the verification team to verify the functionality and correctness of the design.
• You collaborate with implementation to achieve your timing and area.
• You produce quality RTL on schedule meeting PPA goals.
• You engage with performance and power team on achieving performance and power goals.
• You partner with the physical design and CAD team to resolve implementation level details.
• You help mentor junior engineers in the team.

Skills and Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD.
• Strong background owning and driving the RTL design of various sub-blocks of the coherent interconnect or memory controller or LLC for the high performance digital designs.
• Demonstrated experience of successful Architectural through RTL design experience on high performance digital designs.
• Verilog expertise is required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.
• Knowledge of system caches and directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience in leading and mentoring a team of engineers.
• Knowledge of in Arm AMBA5 CHI, AMBA4 ACE or AXI coherent interconnect and bus protocols.
• Knowledge of memory subsystem design including coherent cache design.
• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, global team.

Preferred candidates will possess the following:

• Knowledge of Verilog/VHDL, scripting, STA, DFT, ECO flows.
• Proficient in AMBA, ACE, AXI, CHI protocols.
• Knowledge of memory controller and either coherent interconnect or cache design.
• Knowledge of memory subsystem, coherency, directory snoop filter protocols.
• Familiarity with different on-chip network topologies: mesh, ring, crossbar.
• Experience with a scripting language like Perl or Python.
• Energetic, curiosity, and passion in logic design.
• Good written and verbal communication skills.
• Efficient digital design techniques.

Our Team

Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.

With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,557 and $305,414. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

U.S. Export Control

This position requires the ability to access information subject to U.S. export control restrictions. Applicants must have the ability to access export-controlled information or be eligible to receive a government authorization to access export-controlled information.

Trade Secrets

By submitting an application, you [applicant] agree[s] not to disclose to Samsung, or induce Samsung to use, any confidential or proprietary information (including trade secrets) belonging to any current or previous employer or other person or entity.

#SARC #ACL #Hybrid