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A leading semiconductor company is seeking a Senior ASIC Synthesis Engineer. This role involves leading RTL-to-gates implementation, mentoring junior engineers, and collaborating across teams. Candidates should have over 8 years of ASIC synthesis experience, expertise in Cadence or Synopsys tools, and a deep understanding of SDC constraint writing. This position offers a salary between $140,000 to $160,000 plus comprehensive benefits.
Position: Senior ASIC Synthesis Engineer
Location: Remote (within the U.S.)
Employment Type: Full-time (Salary + Benefits + Bonus) or Contractor
Eligibility: U.S. Citizens or Green Card holders.
Description:
Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX. Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization. Act as a technical mentor for junior engineers, ensuring high-quality netlists with robust DFT integration. Collaborates cross-functionally with RTL, verification, and backend teams to minimize ECO cycles and accelerate signoff readiness.
Requirements:
The anticipated annual base salary for this position is between $140,000 to $160,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
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