SoC Verification Engineer — Hybrid Role

Intel Corporation; Austin (TX); Hybrid; USD 142,000 - 200,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Job summary

Intel Corporation in Austin, Texas, is seeking a SoC Design Verification Engineer to help ensure complex chip designs meet specifications and deliver high performance in presilicon and postsilicon contexts.

You will design scalable verification plans, build test benches, run emulation and simulation, and work with architects, RTL, and tool vendors to improve reliability. A strong background in OVM/UVM and a 3+ year track record is expected, with a hybrid work model in the US.

Qualifications

• Bachelor's degree with 3+ years of SoC design verification experience or a Master’s with 2+ years.
• Demonstrated expertise in OVM/UVM methodologies, debugging, and test planning.
• PhD is also acceptable for the highest tier.

Responsibilities

• Define and develop scalable verification plans for blocks, subsystems, and SoCs.
• Create test benches and verification environments aligned to microarchitecture specs.
• Execute verification plans using emulation and system simulation models.
• Debug and root cause issues in presilicon environments with corrective actions.
• Collaborate with architects, RTL developers, postsilicon, and physical design teams.
• Document and maintain test plans and drive technical reviews.
• Integrate security coverage activities within test plans (regression and debug).

Skills

OVM/UVM

Debugging

Test planning

Team collaboration

Education

Bachelor's degree in Electrical/Computer Engineering/CS or related

Master's degree in Electrical/Computer Engineering/CS or related

PhD in Electrical/Computer Engineering/CS or related

Tools

Emulation models

System simulation tools

Presilicon verification

Job description

Intel Corporation in Austin, Texas, is seeking a SoC Design Verification Engineer to help ensure complex chip designs meet specifications and deliver high performance in presilicon and postsilicon contexts.

You will design scalable verification plans, build test benches, run emulation and simulation, and work with architects, RTL, and tool vendors to improve reliability. A strong background in OVM/UVM and a 3+ year track record is expected, with a hybrid work model in the US.