SoC Logic Design Engineer

Intel Corporation; Folsom (CA); On-site; USD 106,000 - 149,000; Full time

Job summary

Intel Corporation seeks a SoC Logic Design Engineer to contribute to design, coding, and simulation of system-on-chip blocks. You will integrate IP blocks into full chip designs, and ensure timing, power, area, and security objectives are met across DCG projects.

You will work with RTL coding (Verilog/VHDL), in the context of advanced IP integration and verification, with a focus on quality and efficiency for data-center products.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field, with 0–1 years of hands-on experience OR a Master’s degree with no prior professional experience.
• Advanced RTL coding in Verilog or VHDL.
• Familiar with synthesis, timing, and simulation tools (e.g., Design Compiler, Xcelium).
• Understanding PCP/power, performance, and area optimization in SoC designs.
• Basic timing analysis knowledge.

Responsibilities

• Design and implement logic for SoC blocks and subsystems using RTL coding techniques.
• Integrate IP blocks and subsystems into full chip SoC designs, ensuring seamless functionality.
• Conduct quality checks across RTL, timing, power, and area convergence.
• Optimize logic designs to meet power, performance, area, and timing targets.
• Review verification plans and resolve failing RTL tests; collaborate with IP providers for SoC validation.
• Follow secure development practices to meet security objectives.
• Drive QA standards for IP and SoC handoff.

Skills

RTL coding (Verilog/VHDL)

Analyzing RTL tests

Education

Bachelor’s degree in EE/CE

Tools

Synopsys Design Compiler

Cadence Xcelium

Job description

Job Details

Job Description:

As a SoC Logic Design Engineer, you will actively contribute to the development, coding, and simulation of system-on-chip (SoC) designs. You will integrate logic from various IP blocks and subsystems into a complete chip design, ensuring power, performance, area, and timing goals are met. Your work will directly impact the delivery of cutting-edge, high-quality SoC solutions that drive advancements in technology and innovation.

The role is part of Intel’s Data Center Group (DCG), which focuses on delivering advanced solutions that enable data-centric computing for global industries. As a member of this organization, you will collaborate on projects that shape the performance, security, and efficiency of Intel’s data center offerings, contributing to the broader infrastructure required for modern computing needs.

The primary responsibilities for this role will include, but are not limited to:

• Design and implement logic for SoC blocks and subsystems using register transfer level (RTL) coding techniques.
• Integrate IP blocks and subsystems into full chip SoC designs, ensuring seamless functionality.
• Conduct quality checks across various aspects of logic design, from RTL coding to timing, power, and area convergence.
• Optimize logic designs to meet power, performance, area, and timing targets.
• Review verification plans and resolve failing RTL tests to ensure correctness of design features. - Collaborate with IP providers to integrate and validate IPs for SoC-level designs.
• Follow secure development practices to meet security objectives and address security threats in designs.
• Drive compliance with quality assurance standards for successful IP and SoC handoff.

Qualifications

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field, with 0 - 1 years of hands-on experience in logic design gained through internships, academic projects, coursework, or hands-on training OR a Master’s degree in Electrical Engineering, Computer Engineering, or related field with no prior professional experience.
• Advanced experience in register transfer level (RTL) coding languages such as Verilog or VHDL.
• Basic knowledge with industry-standard tools for logic design, synthesis, and simulation (e.g., Synopsys Design Compiler, Cadence Xcelium).
• Basic knowledge of power, performance, and area optimization in SoC designs.
• Basic knowledge of timing analysis and static timing tools.

Preferred Qualifications

• Strong analytical and problem-solving skills with attention to detail.
• Effective communication skills to collaborate with cross-functional teams.
• Experience working on academic or industry projects involving SoC design and IP integration.
• Passion for learning and contributing to advancements in semiconductor technology.

Job Type

College Grad

Shift

Shift 1 (United States of America)

Primary Location

US, California, Santa Clara

Additional Locations

US, California, Folsom, US, Oregon, Hillsboro

Position of Trust

N/A

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $105,650.00 - 149,150.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.