SoC Chip Lead

Lattice Semiconductor Corp.; San Jose, Northern (CA, KY); Hybrid; USD 248,000 - 320,000; Full time

Job summary

Lattice Semiconductor Corp. in San Jose seeks a senior SoC Chip Lead to drive multi-site hardware design, tapeout, and architecture tradeoffs for FPGA/SoC products.

You will own system-level modeling, DFx, and cross-functional leadership, partnering with RTL, software, and IP teams to accelerate pre-silicon validation and product delivery.

Qualifications

• BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience.
• Established track record leading programs from concept to tape-out and production release.
• Expertise in SystemVerilog, synthesis, and static timing analysis.
• Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet architectures.
• Own system-level functional and performance modeling across SoC subsystems, RTL correlation and emulation-based pre-silicon validation.
• Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level.
• Experience debugging complex use cases through verification, emulation, and system validation.
• Demonstrated ability to lead geographically distributed, cross-functional engineering teams.
• Strong written and oral communication skills with a history of executive-level presentations.

Responsibilities

• Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D packaging technologies and chiplet-based architectures across program generations.
• Own chip tapeout and chip signoff with full accountability for chip quality.
• Drive cross-functional technical leadership across multiple sites; translate product requirements into clear priorities, tradeoffs, and execution paths.
• Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions across the SoC.
• Lead cycle-approximate performance modeling to enable architectural exploration ahead of RTL availability.
• Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures.
• Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI.
• Engage with leading IP vendors to define and execute the IP roadmap; conduct competitive benchmarking.
• Present project status and technology roadmaps to executive leadership, with a focus on new growth markets and opportunities.
• Apply agentic AI methodologies to scale and accelerate design execution.

Skills

SystemVerilog

Synthesis

Static timing analysis

Performance modeling

Cross-functional leadership

Executive presentations

Communication

Education

BS in Electrical or Computer Engineering

MS/PhD in Electrical or Computer Engineering

Tools

Emulation platforms

Verification tools

Job description

## SoC Chip LeadApply: San Jose, CA: Full time: Posted Today: R-103351# **Lattice Overview**There is energy here...energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.**Job Description:**We are looking for a senior **SoC Chip Lead** to join our San Jose office. **Key Responsibilities** · Lead development of MCMs with FPGA and ASSPs utilizing 2.5D/3D advanced packaging technologies and chiplet-based architectures across multiple program generations· Own chip tapeout and chip signoff with full accountability for chip quality· Drive cross-functional technical leadership across multiple sites; translate product requirements into clear priorities, tradeoffs, and execution paths· Partner with architects, RTL engineers, and software teams to evaluate architecture tradeoffs and drive hardware design decisions across the SoC· Lead cycle-approximate performance modeling to enable architectural exploration ahead of RTL availability and accelerate early software development· Quantify system-level tradeoffs across compute, memory bandwidth, and on-chip interconnect to shape reference architectures and inform long-term silicon strategy· Own system-level debug spanning floor-planning, power distribution, clocking, timing closure, and SI/PI· Engage with leading IP vendors to define and execute the IP roadmap; conduct competitive benchmarking· Present project status and technology roadmaps to executive leadership, with a focus on new growth markets and opportunities· Apply agentic AI methodologies to scale and accelerate design execution**Required Qualifications** · BS/MS/PhD in Electrical or Computer Engineering with 20+ years of FPGA/SoC design experience· Established track record leading programs from concept to tape-out and production release· Expertise in SystemVerilog, synthesis, and static timing analysis· Deep expertise across SoC domains including High-speed interfaces, System Interconnects, Processor subsystems, and 2.5D/3D packaging and chiplet-based architectures· Own system-level functional and performance modeling across SoC subsystems, ensuring RTL correlation and supporting emulation-based pre-silicon validation· Define and own DFx methodology including scan, BIST, and manufacturing test from IP to chip level· Experience debugging complex use cases through verification, emulation, and system validation· Demonstrated ability to lead and grow geographically distributed, cross-functional engineering teams· Strong written and oral communication skills with a history of executive-level presentations **Pay & Benefits**Consistent with Lattice Semiconductor values and applicable law, we provide the following information to promote pay transparency and equity. We have a market-based pay structure which varies by location. Please note that the base pay range is a guideline, and our compensation range reflects the cost of labor in the U.S. geographic market based on the location of the role. Pay within these ranges varies and depends on job-related knowledge, skills, and relevant work experience.For candidates who receive and offer, the starting salary will vary based on various factors including, but not limited to, such qualifications as, skill level, competencies, and work location. The range provided may represent a candidate range and may not reflect the full range for an individual tenured employee.**Base Pay Range**248400In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity. In addition, this role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!**Additional Information:**This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States.