Silicon Design Lead

OpenAI, Inc.; United States; Remote; USD 180,000 - 240,000; Full time

Job summary

OpenAI is seeking a Silicon Design Lead to drive architecture, microarchitecture, and implementation of AI hardware IP and subsystems. You will translate security and functional requirements into efficient silicon, owning decisions from definition to integration.

Part of the role focuses on hardware security in collaboration with OpenAI's Security team, balancing security with performance, power, and area. Comfortable with RTL design and cross-team collaboration is essential.

Qualifications

• Own hardware IP or subsystem designs from definition through integration.
• Translate security requirements into silicon capabilities with performance and power awareness.
• Read, review, and contribute to RTL implementations (Verilog/SystemVerilog).

Responsibilities

• Own architecture, microarchitecture, and implementation of silicon IP and subsystems.
• Define interfaces, data flows, and microarchitectural tradeoffs to meet goals.
• Partner with Security to translate threat models into hardware features.
• Design and integrate hardware security mechanisms including encryption and key management.
• Evaluate tradeoffs to ensure security meets functional and performance needs.
• Collaborate with RTL, verification, firmware, and software teams for integration.
• Review RTL implementations to ensure alignment with architecture.
• Evaluate IP/third-party IP and drive cross-subsystem solutions.

Skills

Silicon IP Architecture

RTL / SystemVerilog

Hardware security

Cross-functional collaboration

Tools

RTL verification tools

Job description

About the Team

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About the Role

We’re looking for a Silicon Design Lead to drive architecture, microarchitecture, and implementation of key IP and subsystems for our AI hardware platforms. You will translate functional, performance, and security requirements into efficient silicon designs, owning technical decisions from architectural definition through implementation and integration.

Part of this role will focus on hardware security implementation in close partnership with OpenAI’s Security team. While the Security team owns the overarching security architecture and requirements, you will translate those requirements into silicon microarchitecture and implementation, balancing security capabilities with performance, power, area, and design complexity. The other part of this role will focus on driving general silicon architecture/microarchitecture.

In this role, you will:

• Own architecture, microarchitecture, and implementation of silicon IP and subsystems, from requirements and design specifications through integration and validation.

• Define hardware interfaces, data flows, and microarchitectural tradeoffs to meet functional, performance, power, and area requirements.

• Partner closely with OpenAI’s Security team to translate security architecture, requirements, and threat models into implementable hardware capabilities.

• Design and integrate hardware security mechanisms, including encryption, key management, access controls, isolation, and data protection across silicon subsystems.

• Evaluate architectural and implementation tradeoffs to ensure security capabilities meet functional and performance requirements.

• Collaborate with silicon architects, RTL, verification, firmware, and software teams to drive subsystem design, integration, and validation.

• Review and contribute to RTL implementations, ensuring designs align with architectural intent and system requirements.

• Evaluate existing and third-party IP, identify architectural or implementation gaps, and drive solutions across subsystem boundaries.

You might thrive in this role if you:

• Have strong experience in silicon IP or subsystem-level architecture, microarchitecture, and implementation.

• Have owned hardware IP or subsystem designs from architectural definition through implementation and integration.

• Have experience implementing hardware security features such as memory encryption, key management, access controls, isolation, or secure boot.

• Understand how to translate functional and security requirements into hardware architectures, interfaces, and microarchitectural specifications.

• Have working knowledge of RTL design and coding proficiency in Verilog or SystemVerilog, with the ability to read, review, and contribute to RTL.

• Can evaluate performance, power, area, and complexity tradeoffs across silicon designs.

• Work effectively across security, silicon architecture, RTL, verification, firmware, and software teams to drive designs from concept through execution.

• Ideally, have broader SoC-level architecture or integration experience, though deep IP or subsystem-level expertise is sufficient.

To comply with U.S. export control laws and regulations, candidates for this role may need to meet certain legal status requirements as provided in those laws and regulations.

About OpenAI

OpenAI is an AI research and deployment company dedicated to ensuring that general-purpose artificial intelligence benefits all of humanity. We push the boundaries of the capabilities of AI systems and seek to safely deploy them to the world through our products. AI is an extremely powerful tool that must be created with safety and human needs at its core, and to achieve our mission, we must encompass and value the many different perspectives, voices, and experiences that form the full spectrum of humanity.

We are an equal opportunity employer, and we do not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, age, veteran status, disability, genetic information, or other applicable legally protected characteristic.

For additional information, please see .

Background checks for applicants will be administered in accordance with applicable law, and qualified applicants with arrest or conviction records will be considered for employment consistent with those laws, including the San Francisco Fair Chance Ordinance, the Los Angeles County Fair Chance Ordinance for Employers, and the California Fair Chance Act, for US‑based candidates. For unincorporated Los Angeles County workers: we reasonably believe that criminal history may have a direct, adverse and negative relationship with the following job duties, potentially resulting in the withdrawal of a conditional offer of employment: protect computer hardware entrusted to you from theft, loss or damage; return all computer hardware in your possession (including the data contained therein) upon termination of employment or end of assignment; and maintain the confidentiality of proprietary, confidential, and non‑public information. In addition, job duties require access to secure and protected information technology systems and related data security obligations.

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