Silicon Design Engineer — ASIC/RTL Focus

Advanced Micro Devices; Boxborough (MA); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD, Inc. is hiring Silicon Design Engineer to research, design, develop, and test electronic components and systems for semiconductor manufacturing, employing knowledge of electronic theory.

The role includes ASIC development, architecture design, logic design, and system simulation with evaluation of flow from high-level designs to timing and power use. Required: Master’s degree in CS/CE/EE or related field; experience with RTL design, Verilog/VHDL, Front-End EDA tools, CPU architecture, OO

Qualifications

• Master’s degree or foreign equivalent in Computer Science, Computer Engineering, Electrical Engineering, or related field.
• Experience in RTL design, Verilog or VHDL, Front-End EDA tools, CPU architecture, OO design, memory management and Git.
• Experience may be gained through graduate coursework, research, assistantship, or internship.

Responsibilities

• Research, design, develop, and test electronic components and systems for semiconductor manufacturing, including ASIC development.
• Define architecture design, logic design, and system simulation; verify and document ASIC development.
• Evaluate design performance from high-level design to place-and-route, timing and power analysis.
• Apply engineering principles to AMD products with knowledge of circuit boards, processors, chips, and related tools.

Skills

RTL design

Verilog

VHDL

CPU architecture

Object-Oriented Design

Memory management

Git

Education

Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field

Tools

Front-End EDA tools

Job description

AMD, Inc. is hiring Silicon Design Engineer to research, design, develop, and test electronic components and systems for semiconductor manufacturing, employing knowledge of electronic theory.

The role includes ASIC development, architecture design, logic design, and system simulation with evaluation of flow from high-level designs to timing and power use. Required: Master’s degree in CS/CE/EE or related field; experience with RTL design, Verilog/VHDL, Front-End EDA tools, CPU architecture, OO