Server HSIO Signal Integrity Engineer

AMD; Santa Clara (CA); On-site; USD 120,000 - 225,000; Full time

Job summary

AMD is seeking a HSIO Signal Integrity Lead Engineer to drive system-level design and support for EPYC products. The ideal candidate will have a Master's degree and extensive experience in signal integrity and HSIO protocols. You will collaborate closely with various teams to ensure design integrity and performance.

Qualifications

• Deep understanding of industry HSIO protocols like PCIe, USB, SATA, and Ethernet.
• 8+ years of experience with system-level SIPI analysis.

Responsibilities

• Lead pathfinding activity for next generation HSIO interface.
• Manage system level signal integrity analysis and propose solutions.

Skills

Signal Integrity

System-Level Design

Signal Integrity Analysis

Electromagnetic Modeling

Education

Master's degree in Electrical/Electronic Engineering

Job description

1 week ago Be among the first 25 applicants

This range is provided by AMD. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

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Server HSIO Signal Integrity Lead Engineer



The Role

AMD has an opening for HSIO Signal Integrity lead engineer in Server Division working on system level signal integrity design and customer support for EPYC products.

The Person

As a HSIO signal integrity lead engineer on AMD server platform team, you will own simulation methodology, product signal integrity sign off and post si correlation and debugging. you will be directly working together with silicon architecture team, package design team and platform team to influence the design of server products. The main focus will be on system level SI design to meet HSIO interface timing. For post-silicon stage, you will work with electrical validation team for passive and active correlation to build future simulation methodology confidence.

Key Responsibilities

• Lead pathfinding activity for next generation HSIO interface enabling from signal integrity perspective
• Lead HSIO SI simulation methodology development/improvement
• Lead sever product system level signal integrity analysis and propose enabling solutions to meet interface timing
• Collaborate with electrical validation for post silicon correlation
• Lead SI related post silicon debugging
• Work closely with the customer support organization to support customers with signal integrity issues
  
  
  

Qualifications

• Deep understanding of industry HSIO protocols like PCIe 4/5/6/7, USB, SATA and Ethernet
• Deep understanding HSIO system timing allocation and component impact.
• Deep System-level signal integrity and power integrity understanding including silicon, package, and board.
• Experience with Electromagnetic modeling of 3-D structures.
• Candidate must possess a Master's degree in Electrical/Electronic Engineering or equivalent with desired experience in analog/logic validation and characterization.
• 8+ years of experience with component and system level SIPI analysis
• Experience with hardware architecture
  
  
  

Location:

Santa Clara, CA

Austin, TX

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Industries

  Semiconductor Manufacturing

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