Senior Wireless PHY/MAC Design Engineer

InnoPhase IoT, Inc.; San Jose (CA); On-site; USD 216,000 - 220,000; Full time

Job summary

Innophase IOT, Inc. in San Jose, CA is seeking a Principal Engineer for PHY/MAC design to drive end-to-end wireless system development. You will work across the entire signal chain from channel modeling to protocol implementation and DSP optimization.

The role requires a master's degree in EE and up to 15% domestic travel. Expect leadership in RTL design, verification, and collaboration with multiple teams to meet power, timing, and size targets.

Qualifications

• Masters degree in Electrical Engineering, or related field, plus ten years of relevant experience.
• Experience in ASIC development and/or FPGA prototyping.
• RTL design using Verilog, SystemVerilog.
• Knowledge of Digital Signal Processing theory and mapping to design.
• Experience with WiFi PHY or other physical layers.
• Familiarity with timing closure and synthesis for FPGA/ASIC.

Responsibilities

• Develop end-to-end simulation frameworks for wireless systems.
• Cover signal chain from channel modeling to PHY/MAC protocols and DSP algorithms.
• Develop and refine DSP engines for wireless systems.
• Create micro-architecture and SystemVerilog RTL for targets.
• Analyze bottlenecks and provide micro-architectural feedback.
• Develop and refine design, verification, and analysis tools and flows.
• Collaborate with Verification/Validation on test plans and coverage.
• Work with Physical Design on floorplanning and timing closure.

Skills

ASIC development

RTL design

WiFi PHY

Digital signal processing

Education

MS in Electrical Engineering

Tools

VCS

Verdi

Spyglass

Job description

Innophase IOT, Inc. in San Jose, CA is seeking a Principal Engineer for PHY/MAC design to drive end-to-end wireless system development. You will work across the entire signal chain from channel modeling to protocol implementation and DSP optimization.

The role requires a master's degree in EE and up to 15% domestic travel. Expect leadership in RTL design, verification, and collaboration with multiple teams to meet power, timing, and size targets.