Senior Wafer & FPA Process Engineer

Safran Defense & Space, Inc.; Camarillo (CA); On-site; USD 135,000 - 185,000; Full time

Job summary

Safran Defense & Space, Inc. is seeking a Senior Wafer & FPA Process Engineer to own and improve manufacturing processes for III-V materials and FPA back-end workflows.

You will apply DOE and SPC, mentor staff, and drive yield, reliability, and process control across R&D and production environments. The role requires strong background in semiconductor fabrication, data analysis, and documentation, with a focus on safe chemical handling and EHS conformity.

Qualifications

• Bachelor's degree in Electrical Engineering or related field; MS/PhD preferred.
• Experience with DoE and SPC applied to semiconductor processes.
• Experience in microelectronics and wafer fabrication.
• Ability to document tests and create process instructions.

Responsibilities

• Develop and optimize wafer-level and FPA-level fabrication processes for infrared detectors.
• Develop semiconductor wafer processes for III-V materials (InP, GaAs, InGaAs, GaSb).
• Develop and sustain FPA-level processes, including indium bump deposition, underfill, and substrate thinning/removal.
• Develop back-end processes including wafer dicing, die-level cleaning, and FPA inspection and screening.
• Perform failure analysis and root-cause investigations on wafer- and FPA-level yield issues and implement corrective actions.
• Create process travelers and work instructions with clear instructions.
• Track processes and make notes via process travelers.
• Run designed experiments to improve process reproducibility and increase yield.
• Participate in device test data reviews and suggest process improvements to improve device performance.
• Provide engineering and operator oversight.
• Mentor and train operators, technicians, and junior engineers in process execution and cleanroom best practices.
• Ensure safe handling of process chemicals and compliance with cleanroom protocols and EHS requirements.
• Perform other duties as assigned.

Skills

DOE

SPC

Data analysis

Presentation skills

Mentoring

Education

Bachelor's degree in Electrical Engineering

MS or PhD preferred

Tools

MS Office

MATLAB

Python

Mask design software

Job description

Senior Wafer & FPA Process Engineer

Responsible for the development, ownership, and continuous improvement of manufacturing processes—spanning R&D and production—for III‑V semiconductor materials (GaAs, InP, InGaAs, GaSb) used in infrared detector array fabrication, and for focal plane array (FPA) back‑end processes including hybridization and substrate removal that convert detector arrays into finished sensor products. The role applies design of experiments (DOE) and statistical process control (SPC) methodologies to drive yield and reproducibility, and serves as a senior technical resource within the process engineering team, including mentorship of operators, technicians, and junior engineers.

Responsibilities

• Develop and optimize wafer‑level and FPA‑level fabrication processes for infrared detectors and other optoelectronic devices
• Develop semiconductor wafer processes for III‑V materials (InP, GaAs, InGaAs, GaSb), including photolithography, wet/dry etch, metal and dielectric deposition, and surface preparation/passivation
• Develop and sustain FPA‑level processes, including indium bump deposition, underfill, and substrate thinning/removal
• Develop back‑end processes including wafer dicing, die‑level cleaning, and FPA inspection and screening
• Perform failure analysis and root‑cause investigations on wafer‑ and FPA‑level yield issues and implement corrective actions
• Create process travelers and work instructions with clear instructions
• Track processes and make notes via process travelers
• Run designed experiments to improve process reproducibility and increase yield
• Participate in device test data reviews and suggest process improvements to improve device performance
• Provide engineering and operator oversight
• Mentor and train operators, technicians, and junior engineers in process execution and cleanroom best practices
• Ensure safe handling of process chemicals and compliance with cleanroom protocols and EHS requirements
• Perform other duties as assigned

Required Qualifications

• B.S. in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field; M.S. or Ph.D. preferred
• Experience with the operation of nanofabrication equipment including photolithographic stepper, metal deposition, wet/dry etching, SEM, and plasma deposition machines
• 7–10+ years of experience in microelectronic semiconductor fabrication and wafer handling techniques
• Proven track record of developing solutions to process development problems
• Experience with Design of Experiments and Statistical Process Control
• Ability to understand and analyze data related to semiconductor device performance
• Ability to convey data analysis in an accurate and concise format and develop and deliver presentations
• Experience with creating reports, documenting tests, and creating and reviewing process work instructions
• Requires U.S. Citizenship or Permanent Resident Status

Preferred Qualifications

• Familiarity with infrared detector technologies (InGaAs SWIR, MWIR, LWIR) and FPA/ROIC architectures
• Experience in mask design and with mask design software
• Program or project management experience
• Ability to mentor team members
• Works well in a fast‑paced team environment
• Strong organizational and communication skills
• Excellent writing skills and computer capabilities (MS Office, MATLAB, Python)
• Experience in MES, computer programming and software development
• Ability to complete tasks with minimal supervision
• Experience working in an ITAR environment

Travel

Little travel is expected for this position, although some out‑of‑area and overnight travel may be required.

Salary

$135,000–$185,000 annual salary, plus participation in individual performance bonus plan.

Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions of the role.

EOE/AA/M/F/Vets – US Protected Individual status required (US citizen, lawful permanent resident, asylee, refugee or temporary resident as defined under 8 U.S.C. 1160(a)).