Senior Wafer & FPA Process Engineer

Safran Group; Camarillo (CA); On-site; USD 135,000 - 185,000; Full time

Job summary

Safran Defense & Space, Inc. in the United States seeks a Senior Wafer & FPA Process Engineer to lead development and optimization of III-V semiconductor materials and focal plane array back-end processes, spanning R&D and production.

The role applies DOE and SPC methodologies to drive yield and reproducibility, and serves as a senior technical resource within the process engineering team, including mentoring operators, technicians, and junior engineers.

Qualifications

• Experience with design of experiments and statistical process control.
• Experience in microelectronic semiconductor fabrication and wafer handling.
• Ability to develop solutions to process development problems.

Responsibilities

• Develop and optimize wafer-level and FPA-level fabrication processes for infrared detectors and other optoelectronic devices.
• Develop semiconductor wafer processes for III-V materials (InP, GaAs, InGaAs, GaSb).
• Develop and sustain FPA-level processes, including indium bump deposition, underfill, and substrate thinning/removal.
• Develop back-end processes including wafer dicing, die-level cleaning, and FPA inspection and screening.
• Perform failure analysis and root-cause investigations and implement corrective actions.
• Mentor and train operators, technicians, and junior engineers in process execution and cleanroom practices.

Skills

DOE/Statistical process control

Data analysis

Education

B.S. in Electrical Eng.

Tools

Photolithographic stepper

Metal deposition

Wet/dry etching

SEM

Plasma deposition

Job description

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About Our Mission

Join the forefront of innovation and make an impact at Safran Defense & Space, Inc.!

Safran Defense & Space Inc. (Safran DSI), headquartered in Arlington, Va., is a leading U.S. aerospace company dedicated to supporting national defense and space missions. As a trusted partner to the U.S. armed forces, government agencies, and commercial sectors, Safran DSI delivers advanced technology solutions through its specialized business units: Assured PNT, Attollo Engineering, Geospatial AI, Optronics, Space Solutions, and Testing & Telemetry.

Attollo Engineering is a designer and manufacturer of cutting‑edge infrared cameras and laser sensor systems for defense and industrial applications. Leveraging extensive expertise in the electro‑optical market, systems design, and packaging, Attollo delivers superior solutions for system integrators, original equipment manufacturers, and custom applications. Their commitment to quality engineering empowers Safran DSI to provide innovative and reliable technology to its partners.

If you’re ready to join our mission and serve those who serve, Safran DSI is the perfect place for you to take your career to the next level. Make a real difference and be part of something extraordinary. Apply now and help us build the future of defense and space.

Position Profile

The Senior Wafer & FPA Process Engineer is responsible for the development, ownership, and continuous improvement of manufacturing processes — spanning R&D and Production — for III‑V semiconductor materials (GaAs, InP, InGaAs, GaSb) used in infrared detector array fabrication, and for focal plane array (FPA) back‑end processes including hybridization and substrate removal that convert detector arrays into finished sensor products. The role applies design of experiments (DOE) and statistical process control (SPC) methodologies to drive yield and reproducibility, and serves as a senior technical resource within the process engineering team, including mentorship of operators, technicians, and junior engineers.

Responsibilities

• Develop and optimize wafer‑level and FPA‑level fabrication processes for infrared detectors and other optoelectronic devices
• Develop semiconductor wafer processes for III‑V materials (InP, GaAs, InGaAs, GaSb), including photolithography, wet/dry etch, metal and dielectric deposition, and surface preparation/passivation
• Develop and sustain FPA‑level processes, including indium bump deposition, underfill, and substrate thinning/removal
• Develop back‑end processes including wafer dicing, die‑level cleaning, and FPA inspection and screening
• Perform failure analysis and root‑cause investigations on wafer‑ and FPA‑level yield issues and implement corrective actions
• Create process Travelers and Work Instructions with clear instructions
• Track processes and make notes via process travelers
• Run designed experiments to improve process reproducibility and increase yield
• Participate in device test data reviews and suggest process improvements to improve device performance
• Provide engineering and operator oversight
• Mentor and train operators, technicians, and junior engineers in process execution and cleanroom best practices
• Ensure safe handling of process chemicals and compliance with cleanroom protocols and EHS requirements
• Perform other duties as assigned

What You’ll Need to Be Successful

• B.S. in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field; M.S. or Ph.D. preferred
• Experience with the operation of nanofabrication equipment including Photolithographic stepper, metal deposition, wet/dry etching, SEM, and plasma deposition machines
• 7‑10+ years of experience in microelectronic semiconductor fabrication and wafer handling techniques
• Candidate should possess a proven track record of developing solutions to process development problems
• Experience with Design of Experiments and Statistical Process Control
• Ability to understand and analyze data related to semiconductor device performance
• Ability to convey data analysis in an accurate and concise format and developing and delivering presentations
• Experience with creating reports, documenting tests, and creating and reviewing process work instructions
• Requires U.S. Citizenship or Permanent Resident Status required.

Ideally You’ll Also Have

• Familiarity with infrared detector technologies (e.g., InGaAs SWIR, MWIR, LWIR) and FPA/ROIC architectures
• Experience in mask design and with mask design software
• Program or project management experience
• Ability to mentor team members
• Works well in a fast‑paced team environment
• Strong organizational and communication skills
• Excellent writing skills and computer capabilities (MS Office, MatLab, Python)
• Experience in MES, computer programming and software development
• Ability to complete tasks with minimal supervision
• Experience working in an ITAR environment

Travel

Little travel is expected for this position, although some out-of-area and overnight travel may be required

Salary Range

$135,000‑$185,000 annual salary, plus participation in individual performance bonus plan.

Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions of the role.

EOE/AA/M/F/Vets – US Protected Individual status required (US citizen, lawful permanent resident, asylee, refugee or temporary resident (as defined at 8 USC 1160(a).

Nearest Major Market: Ventura
Nearest Secondary Market: Oxnard