Senior UVM Verification Engineer (IP-Level)

MooresLabAI; Town of Texas (WI); On-site; USD 139,000 - 241,000; Full time

Job summary

MooresLabAI is seeking a Senior UVM Verification Engineer to lead IP verification using AI technology. Ideal candidates will have extensive experience in ASIC/FPGA verification and proficiency with SystemVerilog and UVM. Join our agile team to revolutionize chip design and contribute to innovative projects that redefine industry standards.

Benefits

Competitive salary and equity packages

Professional development and mentorship

Collaborative and technically driven culture

Qualifications

• 8+ years of experience in ASIC/FPGA verification.
• Strong knowledge of IP-level verification.
• Experience with assertion-based verification and formal tools is a plus.

Responsibilities

• Develop UVM testbenches for IP-level verification.
• Mentor junior verification engineers.
• Build AI infrastructure for coverage closure.

Skills

Debugging skills

Scripting abilities

Knowledge of verification plans

Education

B.S./M.S. in Electrical Engineering

Tools

SystemVerilog

UVM

EDA tools

Job description

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Company Overview:

We’re a fast-growing startup on a mission to revolutionize chip development through cutting-edge AI. Our team is small, agile, and deeply committed to building a groundbreaking product that will redefine how chips are designed.

Role Overview:

As a Senior UVM Verification Engineer, you will lead the IP verification components of our product using advanced UVM-based testbenches and AI technology.You will work closely with AI engineers and frontend engineers to ensure that the generated UVM testbench meets quality and coverage goals.

Key Responsibilities:

Develop UVM testbenches for IP-level verification using MooresLabAI VerifAgent. Enable AI technology to define and implement verification plans based on functional specifications and design documents.

Use AI agents to create, run, and debug constrained-random testcases and functional coverage models.

Develop reusable components including agents, drivers, monitors, and scoreboards using AI.

Build AI infrastructure for coverage closure and debug failures to root cause.

Mentor junior verification engineers and contribute to team best practices.

Requirements:

B.S./M.S. in Electrical Engineering, Computer Engineering, or related field.

8+ years of experience in ASIC/FPGA verification using SystemVerilog and UVM.

Strong knowledge of IP-level verification and protocol-based design (e.g., AXI, AHB, PCIe, USB, Ethernet, etc.).

Proven experience writing testplans, developing scoreboards, drivers, monitors, and coverage models.

Familiarity with assertion-based verification and formal tools is a plus.

Hands-on experience with EDA tools (Synopsys, Cadence, Mentor).

Strong debugging skills and scripting abilities (Python, Perl, Make, etc.).

Excellent verbal and written communication skills.

Preferred Qualifications:

Previous experience with these protocols:

Prior contributions to verification methodology development or tool flow automation.

What We Offer:

Competitive salary and equity packages

Collaborative and technically driven culture

Opportunities to work on leading-edge AI technology and IP designs

Professional development and mentorship

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Full-time

Job function

• Job function

  Quality Assurance

• Industries

  Semiconductor Manufacturing

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