Senior UVM Digital Verification Engineer

Draper; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Benefits offered by this job

Work-life balance programs

Flexible work options

Employee clubs

Job summary

Draper in Cambridge, MA seeks a Senior UVM Digital Verification Engineer to tackle novel verification challenges for FPGAs and ASICs. You will apply modern verification strategies to embedded security, cryptography, and signal processing in a collaborative, multi-disciplinary setting.

You will develop verification plans, create UVM agents, and work with RTL designers to resolve issues while mentoring junior engineers. A strong background in SystemVerilog and Linux is required.

Qualifications

• Bachelor's degree in an engineering field; Master’s preferred.
• Experience with UVM-based verification and RTL design.
• Strong knowledge of SystemVerilog and verification methodologies.

Responsibilities

• Develop verification approaches and verification plans.
• Create and maintain UVM agents for proprietary buses.
• Instantiate VIPs for industry-standard buses and debug issues.
• Mentor junior engineers and perform code reviews.
• Collaborate across multidisciplinary teams including RTL designers.

Skills

UVM

SystemVerilog

Formal Analysis

Python

Linux

DDR3/DDR4

AXI/AMBA

Education

Bachelor's degree in Electrical Engineering

Master's degree

Tools

QuestaSim

Xcelium

VCS

Job description

Overview:Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit www.draper.com.Job Description Summary:Draper’s Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.Job Description:Duties/ResponsibilitiesPerforms analysis approaches for a particular problem and independently execute assignments.Independently execute system engineering lifecycle assignments; concept and architecture design, integration, testing and operation.Drive solutions to complex problems with limited direction – contribute to task planning and test development, propose ways forward, and adapt appropriately to changes in program requirementsDemonstrated ability to lead small teams (fewer than five people). Seeks to align team towards program goals and builds trust within the team.Able to provide insight and suggest design modifications based on analysis outcomes, and to apply analysis techniques across a range of technical challenges.Identify program/system-level technical risks and develop and execute mitigation strategies for them.Actively mentor less experienced engineers and provide thoughtful, constructive feedback.Work in a collaborative multidisciplinary environment including stakeholders and external partners.Contribute to translation of requirements into technical and architectural decisions.Skills/AbilitiesExcellent mathematical skills.Thorough understanding of engineering theories and procedures.Ability to collaborate within a diverse and multidisciplinary team.Excellent verbal and written communication skills.Excellent organizational skills and attention to detail.Excellent time management skills with the proven ability to meet deadlines.Demonstrated knowledge of multiple problem domains, with ability to quickly become knowledgeable in new domains.Identify and develop relevant modeling and analysis techniques, and develop or integrate multi-domain qualitative models.Ability to present results that support system-level analysis, performance trade-offs, and decision-making is critical, thus communications and interpersonal skills are highly valued in this role.The ability to communicate technical concepts effectively with customers, engineers, managers, and other stakeholders of all relevant disciplines.Flexibility to multi-task and adapt to evolving priorities.EducationBachelor’s degree in Aerospace, Electrical, Mechanical, or other relevant Engineering field. Master's degree preferred.ExperienceRequires 5-7 years experience in systems analysis or related.Experience in integrating descriptive modeling tools with other simulation tools.Additional Job Description:You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.Develop verification and test plansDevelop UVM Agents for proprietary busesInstantiate VIPs for industry standard busesWork in both block-level/chip-level UVM testbench environmentWork with RTL designers to resolve simulation issuesImplement cover groups according to design requirementsWork on code and functional coverage closures to achieve 100%Perform code reviews and to mentor junior engineers in the groupFluent in System Verilog including SVARecent experience with UVM/UVMFFamiliarity with at least one major industry simulator (Questasim, Xcelium, VCS)Familiarity with at least one IEEE bus standardExperience with DDR3/DDR4, Amba Axi protocolsFirm grasp of constrained-random testing and coverage-driven verificationExperience with formal analysisPractice using Python, Perl, Bash or other scripting languagesAbility to work in a Linux environmentStrong analysis and problem-solving skillsApplicants selected for this position will have or be able to obtain and maintain a government security clearance.Connect With Draper for Future Opportunities! If you don't find the right posting in our Career Opportunities, you may submit your resume for future consideration.Job Location - City:CambridgeJob Location - State:MassachusettsJob Location - Postal Code:02139-3563The US base salary range for this full-time position is$82,300.00 - $220,000.00Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Union ranges will be in compliance with the collective bargaining agreement's approved rates by location and role. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and does not include bonuses or benefits.Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now www.draper.com/careers.Draper is committed to creating an inclusive environment. We understand the value of inclusivity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact [e-mail].