Senior System Level Test Engineer - LPU

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 196,000 - 310,500; Full time

Benefits offered by this job

Equity

Comprehensive benefits package

Competitive salary based on location

Job summary

NVIDIA Gruppe is seeking a Senior System Level Test Engineer to drive the design, automation, and validation of system-level tests for high-performance GPUs and SOCs. You will collaborate with various teams to ensure robust testing and optimal system performance.

The ideal candidate will have a MS/PhD in Electrical Engineering or a related field, and over 12 years of experience in system-level testing. A competitive salary and comprehensive benefits package are offered.

Qualifications

• 12+ years of experience in system-level test and validation.
• Experience testing and characterizing high-speed I/Os.
• Experience driving SLT testing and deployment for HVM.

Responsibilities

• Lead the design, automation, and validation of System Level Tests for HVM.
• Develop and integrate test flows, scripts, and automation.
• Collaborate with architecture and validation teams to deliver production-ready SLT solutions.

Skills

C#

C/C++

Perl

Python

.NET framework

System-level testing

High-power SOCs testing

Network connectivity

Education

MS/PhD in Electrical Engineering, Computer Science, or Computer Engineering

Job description

Senior System Level Test Engineer

Join NVIDIA’s senior engineering team to push the frontiers of system‑level testing for leading GPUs, SoCs, and ASICs.

Responsibilities

• Lead the design, automation, and validation of System Level Tests (SLT) for High Volume Manufacturing (HVM) on complex, high‑power, high‑speed SOCs.
• Develop and integrate test flows, scripts, and automation to ensure robust SLT coverage and seamless communication between test controllers and peripherals.
• Partner with system architecture, chip design, and validation teams to define and deliver production‑ready SLT and HVM test solutions.
• Drive custom SLT development to optimize system performance, power efficiency, and test coverage.
• Oversee handler selection, enablement, and hardware integration – including PCB design, socket selection, and temperature control systems.
• Improve manufacturing test quality by enhancing test correlation, yield, and reliability across NPI, HVM and RMA processes.
• Collaborate closely with OSATs on production enablement, sustaining, yield analysis and DPPM reduction initiatives.
• Support silicon qualification and reliability testing (HTOL, Burn‑in) at the system level.

Qualifications

• MS/PhD in Electrical Engineering, Computer Science, Computer Engineering, or equivalent experience.
• 12+ years of experience in system‑level test, system validation, and/or bench testing.
• Experience with new silicon bring‑up at the system level.
• Experience driving SLT testing and deployment for HVM.
• Experience testing and characterizing high‑power SOCs and high‑speed I/Os.
• Knowledge of network topology and experience in network connectivity.
• Proficiency in C#, C/C++, Perl, Python, and .NET framework.
• Experience in security provisioning and fuse programming implementation.

Benefits

• Competitive salary based on location, experience, and comparable positions.
• Base salary range: $196,000–$310,500 (Level5); $232,000–$368,000 (Level6).
• Equity and comprehensive benefits package.
• Additional information about benefits is available at www.nvidiabenefits.com.

Equal Opportunity Employment

NVIDIA is committed to fostering a diverse work environment and is proud to be an equal‑opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.