Senior Staff Engineer: Hybrid HPC/DB Kernel

Circana

United States

Hybrid

USD 140,000 - 210,000

Full time

5 days ago
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Benefits offered by this job

Bonus pay
Medical/dental/vision insurance
401(k)
Paid time off

Job summary

Circana is seeking a Senior Staff Engineer to drive the evolution of a high-performance, massively parallel processing database engine that powers large-scale retail analytics. You will bridge HPC and big data, delivering low-latency kernels on multi-core, vectorized hardware and distributed networks.

You will contribute to architecture, implement production-grade backend code, and optimize performance across clusters, with opportunities to mentor others and influence platform capabilities.

Qualifications

  • Bachelor's degree in CS; Master's in HPC/Big Data preferred for senior roles.
  • 8+ years of production experience in C++ (C++17/20/23).
  • Experience with MPI, OpenMP, and MapReduce frameworks.
  • Hardware-aware optimization and SIMD intrinsics knowledge.
  • Strong debugging, performance tuning, and problem-solving skills.
  • Familiarity with distributed database internals and large-scale systems.

Responsibilities

  • Architect core kernels and roadmap for a distributed database engine.
  • Write and optimize backend C++ code for low latency and high throughput.
  • Design MPP execution plans across many nodes using MPI/OpenMP.
  • Profile and optimize with SIMD/vectorization and cache locality.
  • Develop ultra-low latency cluster communications and DP/DMA paths.
  • Build in-database ML framework to reduce data movement.
  • Lead architecture reviews and mentor peers; resolve scale challenges.

Skills

MPI
OpenMP
C++ optimization
Debugging
Performance tuning
Distributed systems
Algorithm design

Education

Bachelor's in Computer Science
Master's in HPC/Big Data

Tools

C++ (C++20/23)

Job description

Circana is seeking a Senior Staff Engineer to drive the evolution of a high-performance, massively parallel processing database engine that powers large-scale retail analytics. You will bridge HPC and big data, delivering low-latency kernels on multi-core, vectorized hardware and distributed networks.

You will contribute to architecture, implement production-grade backend code, and optimize performance across clusters, with opportunities to mentor others and influence platform capabilities.

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