Senior Staff ASIC Physical Design Engineer - Paris, France

Nutanix; San Diego (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading technology company is seeking a Physical Design engineer to join their team, focusing on state-of-the-art wireless technology utilized in top devices globally. The ideal candidate will have extensive experience in physical design processes and demonstrate strong leadership qualities within a dynamic team environment.

Qualifications

• 10+ years of Physical Design / Hardware Engineering experience.
• Strong technical leadership and coaching skills.
• Good understanding of low power designs (LEC/CLP).

Responsibilities

• Complete ownership on PNR implementation.
• Lead a team of Physical Block designers.
• Collaborate with teams to resolve issues and ensure timely project execution.

Skills

Physical Design

Floor Planning

Clock Tree Synthesis

Power Analysis

Low power designs

Unix/Linux

Analytical skills

Education

Bachelor's degree

Master's degree

PhD

Job description

Company:

Qualcomm France S.A.R.L.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

About the Role

Qualcomm modem team is looking for a world-class Physical Design engineer looking to work on cutting edge wireless technology, which will be deployed worldwide in our industry’s leading devices.

Responsibilities include:

• Complete ownership on PNR implementation (Floor Planning, Placement, Clock Tree Synthesis, Post Route, …) and signoff (STA, Power Analysis, Formal Verification, Low power Verification, IR Drop, DRC, LVS, …)
• Leading a team of Physical Block designers
• Working collaboratively with block designers, implementation, and post-silicon teams to resolve issues and ensure timely project execution.

What are we looking for?

• Bachelor/Master’s degree in science, engineering, or related field
• 10+ years of Physical Design / Hardware Engineering experience or related work experience
• Very good knowledge of Floor Planning, PNR and STA flows
• Very good knowledge of Placement/Clock Tree Synthesis (CTS)
• Good understanding of low power designs (LEC/CLP)
• Very good knowledge of sign-off tools (DRC, LVS, IRDrop)
• Experience with ASIC top level (Top level floor planning, pad ring, interface with packaging team)
• Good knowledge on Unix/Linux – TCL fundamentals/scripting
• Strong analytical skills and ability to work in a dynamic and fast paced team environment
• Excellent written and verbal skills
• Strong interpersonal skills and a good team player
• Strong technical leadership and coaching skills

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

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