SENIOR STAFF ANALOG/MIXED-SIGNAL DESIGN ENGINEER (SERDES)
SENIOR STAFF ANALOG/MIXED-SIGNAL DESIGN ENGINEER (SERDES)
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Job Description
Video
San Jose, CA – 100% Onsite (5 days/week)
12 Months (Contract – Possible Extensions)
Samsung is seeking a Senior Staff Analog/Mixed-Signal Design Engineer to join our high-performance design team in San Jose. This role will focus on architecture, design, optimization, and validation of high-speed SerDes transceivers and related analog/mixed-signal IP components. You will contribute to cutting-edge SoC solutions used in next-generation interconnect standards such as PCIe, USB, and UCIe.
Key Responsibilities:
- Architect, design, and optimize analog/mixed-signal circuits for SerDes applications.
- Design components such as bandgap references, LDOs, CTLE, DFE, FFE, PI, IQ generation, and clock distribution networks.
- Collaborate on system-level design and floorplanning with digital and layout teams.
- Supervise and review layout to ensure design meets performance and reliability standards (e.g., ESD, IR drop, EM compliance).
- Contribute to silicon bring-up, validation, and debugging in the lab.
- Work closely with architecture teams to define technical specifications and performance goals.
- Document design architecture, assumptions, and test plans for internal reviews.
Qualifications:
- MS or Ph.D. in Electrical Engineering or a related field.
- 7+ years of industry experience in RF/Analog/SerDes SoC design.
- Strong experience with analog/mixed-signal circuit design including:
- Bandgap, LDO, filters
- ADCs/DACs
- Deep understanding of SerDes architecture and high-speed I/O standards (PCIe, USB, UCIe).
- Knowledge of ESD design practices and chip-level integration considerations.
- Proficiency in EDA tools including Cadence Virtuoso, Spectre, Totem, EMX.
- Skilled in scripting and data analysis using Python, MATLAB, or similar tools.
- Experience with lab equipment and silicon validation is a strong plus.
- Strong collaboration and communication skills to work cross-functionally in a fast-paced environment.
Nice to Have:
- Experience in high-volume production silicon.
- Familiarity with Power/Signal Integrity (PI/SI) simulations.
- Team leadership or mentoring experience.
Why Join?
- Work on cutting-edge SerDes IP and participate in the design of future silicon technologies.
- Be part of a world-class engineering team in a high-impact role.
- Stable 12-month engagement with potential for long-term extension.
Seniority level
Seniority level
Mid-Senior level
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Information TechnologyIndustries
IT Services and IT Consulting
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