Senior SoC Subsystem and I/O Architect - LPU

NVIDIA Gruppe; California (MO); On-site; USD 184,000 - 287,500; Full time

Benefits offered by this job

Comprehensive benefits package

Equity eligibility

Job summary

NVIDIA Gruppe is looking for a Senior SoC Subsystem & I/O Architect to join our ambitious LPU team. In this role, you will define high-level architecture for next-generation AI and high-performance computing products while collaborating with various teams.

We need someone with strong experience in SoC architecture and solid communication skills. The position offers a competitive salary range of $184,000 to $287,500 for Level4, along with a comprehensive benefits package.

Qualifications

• 8+ years of proven experience in SoC architecture.
• Strong understanding of SoC architecture and uncore subsystem development.
• Solid grasp of memory ordering, coherency, and error management.

Responsibilities

• Define high-level SoC subsystem architecture for LPU products.
• Collaborate with IP teams to develop detailed build documents.
• Drive tradeoffs across bandwidth, latency, power, area, timing, and reliability.

Skills

SoC architecture

SubSystem architecture

IO architecture

Interconnect architecture

GPU/CPU architecture

High-performance systems

Education

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science

Tools

C++

SystemC

Python

Job description

We are seeking a Senior SoC Subsystem & I/O Architect to join our ambitious LPU team. The role involves establishing the high‑level architecture for next‑generation AI and high‑performance computing products.

What You’ll Be Doing

• Define high‑level SoC subsystem architecture for LPU products.
• Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware‑facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
• Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink‑C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure.
• Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software‑visible controls.
• Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages.
• Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available.
• Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability.
• Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies.
• Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post‑silicon teams to bring architecture decisions to completion.

What We Need To See

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
• 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high‑performance systems.
• Strong understanding of SoC architecture and uncore subsystem development.
• Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink‑C2C, UCIe, AXI, CHI, or NoC fabrics.
• Experience working from product requirements to architecture requirements and IP/subsystem specifications.
• Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications.
• Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management.
• Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power‑management architecture.
• Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups.

Ways To Stand Out from the Crowd

• Hands‑on experience with LPU, GPU, CPU, AI accelerator, chiplet, or multi‑die SoC architecture.
• Extensive knowledge in PCIe/CXL, NVLink/NVLink‑C2C, UCIe, AXI/CHI, coherent fabrics, NoCs, or chip‑to‑chip links.
• Extensive knowledge in formulating architecture specifications for advanced SoC subsystems.
• Experience building executable functional models directly from product, architecture, or protocol specs.
• Understanding of deep learning workloads, numerics, memory architecture, and bandwidth/latency tradeoffs.
• Experience with boot architecture, reset sequencing, secure boot, RAS, debug, DFT, power sequencing, or post‑silicon validation.

Compensation & Benefits

Base salary ranges from $184,000 to $287,500 for Level4 and $224,000 to $356,500 for Level5. You will also be eligible for equity and a comprehensive benefits package. NVIDIA offers highly competitive salaries and a comprehensive benefits package to support you and your family.

Equal Opportunity Employer

NVIDIA is committed to fostering an inclusive work environment and is proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.