Senior SoC & FPGA Design Engineer (CPLD/FPGA)

Anysilicon; Westford (MA); Hybrid; USD 90,000 - 150,000; Full time

Job summary

Nokia in Westford, MA is seeking a skilled engineer specializing in CPLD/FPGA design to enhance scalable IP routing solutions across network types. You will collaborate with a diverse team to implement high-availability IP routing products.

The ideal candidate has a BS in Computer or Electrical Engineering and at least 3 years in programmable solutions, with strong HDL experience and familiarity with Xilinx/Altera/Lattice toolchains.

Qualifications

• Bachelor’s degree in Computer and/or Electrical Engineering.
• Minimum 3 years of industry experience in developing programmable solutions.
• Experience with CPLD/FPGA design in a production environment.

Responsibilities

• Collaborate with the board design engineering team to create optimal programmable solutions that meet product specifications.
• Draft detailed design, functional, and programming guideline specifications.
• Design, verify, and implement CPLD/FPGA solutions with a focus on cost, testability, and migratability.
• Work with the diagnostic engineering team to support bring-up, DVT, and manufacturing testing.
• Coordinate with the software engineering team for functional testing and feature implementation.
• Stay updated on technological advancements.

Skills

Digital design principles

HDL (VHDL/Verilog/SystemVerilog)

Synthesis tools (Xilinx/Altera/Lattice

Timing and power analysis

Networking interfaces (I2C/SPI/SVID)

Communication skills

Education

Bachelor’s degree in Computer and/or Electrical Engineering

Tools

Xilinx

Altera

Lattice

Job description

Nokia in Westford, MA is seeking a skilled engineer specializing in CPLD/FPGA design to enhance scalable IP routing solutions across network types. You will collaborate with a diverse team to implement high-availability IP routing products.

The ideal candidate has a BS in Computer or Electrical Engineering and at least 3 years in programmable solutions, with strong HDL experience and familiarity with Xilinx/Altera/Lattice toolchains.