Senior SoC Display Subsystem Architect

Apple Inc.; San Diego (CA); On-site; USD 184,700 - 277,600; Full time

Benefits offered by this job

Employee stock program

Comprehensive benefits

Job summary

Apple Inc. in Cupertino, California, is seeking a Display System Engineer to lead the architecture of the SoC display subsystem.

You will collaborate with SoC and fabric architects, software, and system engineers to shape display interfaces, memory pipes, and data flows from concept to production. The role requires deep experience in chip and display subsystem architecture, with a track record of architecture definitions and performance-energy tradeoffs.

Qualifications

• Experience in chip architecture and display subsystem architecture/design.
• Experience in SoC display subsystem architecture and micro-architecture.
• 10+ years of experience in signal/image processing.
• MS or PhD degree.
• Understanding of SoC display sub-system architecture, interface, performance and energy tradeoffs.
• Understanding of display or image technology.
• Expertise in memory subsystem, memory interface, and DMA.
• Architectural modeling ability.
• Strong communication with cross-functional teams.

Responsibilities

• Work closely with SoC and fabric architects, software, and system engineers to architect SoC display subsystem
• Architect display subsystems, including display pipe control, memory, and interfaces
• Provide detailed architectural guidance at all levels of design throughout the design process from concept through production
• Make recommendations on key design tradeoffs across architecture and performance
• Author and maintain the display subsystem architecture specifications

Skills

Signal/image processing

Cross-functional communication

Architectural modeling

Education

MS or PhD degree

Job description

Apple Inc. in Cupertino, California, is seeking a Display System Engineer to lead the architecture of the SoC display subsystem.

You will collaborate with SoC and fabric architects, software, and system engineers to shape display interfaces, memory pipes, and data flows from concept to production. The role requires deep experience in chip and display subsystem architecture, with a track record of architecture definitions and performance-energy tradeoffs.